トップPVスタティック タイミング レポート

PV4 リリース番号: 06

--------------------------------------------------------------------------------
Release 10.1.03 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

E:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise E:/RTL/Project/PV/PV.ise
-intstyle ise -v 3 -s 4 -xml PV PV.ncd -o PV.twr PV.pcf -ucf
E:/RTL/Code/PV/UCF/PV.ucf

Design file:              PV.ncd
Physical constraint file: PV.pcf
Device,package,speed:     xc3s200a,ft256,-4 (PRODUCTION 1.41 2008-07-25)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_pci_clock = PERIOD TIMEGRP "pci_clock" 30 ns HIGH 50%;

 44165 paths analyzed, 3098 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is  15.532ns.
--------------------------------------------------------------------------------
Slack:                  7.440ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/write/out_gray_2 (FF)
  Destination:          fifo/fifo/count/write_address_gray_0_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      1.741ns (Levels of Logic = 0)
  Clock Path Skew:      -0.819ns (1.329 - 2.148)
  Source Clock:         clock_ram rising at 20.000ns
  Destination Clock:    clock_pci rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/write/out_gray_2 to fifo/fifo/count/write_address_gray_0_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y4.YQ        Tcko                  0.676   fifo/fifo/write/out_gray<3>
                                                       fifo/fifo/write/out_gray_2
    SLICE_X0Y6.BY        net (fanout=1)        0.679   fifo/fifo/write/out_gray<2>
    SLICE_X0Y6.CLK       Tdick                 0.386   fifo/fifo/count/write_address_gray_0_3
                                                       fifo/fifo/count/write_address_gray_0_2
    -------------------------------------------------  ---------------------------
    Total                                      1.741ns (1.062ns logic, 0.679ns route)
                                                       (61.0% logic, 39.0% route)

--------------------------------------------------------------------------------
Slack:                  7.516ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/write/out_gray_7 (FF)
  Destination:          fifo/fifo/count/write_address_gray_0_7 (FF)
  Requirement:          10.000ns
  Data Path Delay:      1.678ns (Levels of Logic = 0)
  Clock Path Skew:      -0.806ns (1.316 - 2.122)
  Source Clock:         clock_ram rising at 20.000ns
  Destination Clock:    clock_pci rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/write/out_gray_7 to fifo/fifo/count/write_address_gray_0_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y9.XQ        Tcko                  0.631   fifo/fifo/write/out_gray<7>
                                                       fifo/fifo/write/out_gray_7
    SLICE_X0Y8.BX        net (fanout=1)        0.704   fifo/fifo/write/out_gray<7>
    SLICE_X0Y8.CLK       Tdick                 0.343   fifo/fifo/count/write_address_gray_0_7
                                                       fifo/fifo/count/write_address_gray_0_7
    -------------------------------------------------  ---------------------------
    Total                                      1.678ns (0.974ns logic, 0.704ns route)
                                                       (58.0% logic, 42.0% route)

--------------------------------------------------------------------------------
Slack:                  7.580ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/write/out_gray_1 (FF)
  Destination:          fifo/fifo/count/write_address_gray_0_1 (FF)
  Requirement:          10.000ns
  Data Path Delay:      1.610ns (Levels of Logic = 0)
  Clock Path Skew:      -0.810ns (1.338 - 2.148)
  Source Clock:         clock_ram rising at 20.000ns
  Destination Clock:    clock_pci rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/write/out_gray_1 to fifo/fifo/count/write_address_gray_0_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y4.XQ        Tcko                  0.591   fifo/fifo/write/out_gray<1>
                                                       fifo/fifo/write/out_gray_1
    SLICE_X0Y5.BX        net (fanout=1)        0.676   fifo/fifo/write/out_gray<1>
    SLICE_X0Y5.CLK       Tdick                 0.343   fifo/fifo/count/write_address_gray_0_1
                                                       fifo/fifo/count/write_address_gray_0_1
    -------------------------------------------------  ---------------------------
    Total                                      1.610ns (0.934ns logic, 0.676ns route)
                                                       (58.0% logic, 42.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_video_clock = PERIOD TIMEGRP "video_clock" 13.48 ns HIGH 
50%;

 49346 paths analyzed, 1371 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   9.107ns.
--------------------------------------------------------------------------------
Slack:                  2.801ns (requirement - (data path - clock path skew + uncertainty))
  Source:               video/io/out_negedge_data_1 (FF)
  Destination:          video/data/delay_y_/bram/Mram_data (RAM)
  Requirement:          6.740ns
  Data Path Delay:      3.777ns (Levels of Logic = 0)
  Clock Path Skew:      -0.162ns (0.197 - 0.359)
  Source Clock:         clock_video falling at 6.740ns
  Destination Clock:    clock_video rising at 13.480ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: video/io/out_negedge_data_1 to video/data/delay_y_/bram/Mram_data
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B15.IQ1              Tiockiq               1.016   in_video_data<1>
                                                       video/io/out_negedge_data_1
    RAMB16_X1Y6.DIA6     net (fanout=2)        2.539   video/io/out_negedge_data<1>
    RAMB16_X1Y6.CLKA     Trdck_DIA             0.222   video/data/delay_y_/bram/Mram_data
                                                       video/data/delay_y_/bram/Mram_data
    -------------------------------------------------  ---------------------------
    Total                                      3.777ns (1.238ns logic, 2.539ns route)
                                                       (32.8% logic, 67.2% route)

--------------------------------------------------------------------------------
Slack:                  2.871ns (requirement - (data path - clock path skew + uncertainty))
  Source:               video/io/out_negedge_data_2 (FF)
  Destination:          video/out_pixel_y_5 (FF)
  Requirement:          6.740ns
  Data Path Delay:      3.792ns (Levels of Logic = 0)
  Clock Path Skew:      -0.077ns (0.434 - 0.511)
  Source Clock:         clock_video falling at 6.740ns
  Destination Clock:    clock_video rising at 13.480ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: video/io/out_negedge_data_2 to video/out_pixel_y_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C13.IQ1              Tiockiq               1.016   in_video_data<2>
                                                       video/io/out_negedge_data_2
    SLICE_X25Y39.BX      net (fanout=2)        2.525   video/io/out_negedge_data<2>
    SLICE_X25Y39.CLK     Tdick                 0.251   video/out_pixel_y<5>
                                                       video/out_pixel_y_5
    -------------------------------------------------  ---------------------------
    Total                                      3.792ns (1.267ns logic, 2.525ns route)
                                                       (33.4% logic, 66.6% route)

--------------------------------------------------------------------------------
Slack:                  2.938ns (requirement - (data path - clock path skew + uncertainty))
  Source:               video/io/out_negedge_data_1 (FF)
  Destination:          video/out_pixel_y_4 (FF)
  Requirement:          6.740ns
  Data Path Delay:      3.646ns (Levels of Logic = 0)
  Clock Path Skew:      -0.156ns (0.434 - 0.590)
  Source Clock:         clock_video falling at 6.740ns
  Destination Clock:    clock_video rising at 13.480ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: video/io/out_negedge_data_1 to video/out_pixel_y_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B15.IQ1              Tiockiq               1.016   in_video_data<1>
                                                       video/io/out_negedge_data_1
    SLICE_X25Y39.BY      net (fanout=2)        2.316   video/io/out_negedge_data<1>
    SLICE_X25Y39.CLK     Tdick                 0.314   video/out_pixel_y<5>
                                                       video/out_pixel_y_4
    -------------------------------------------------  ---------------------------
    Total                                      3.646ns (1.330ns logic, 2.316ns route)
                                                       (36.5% logic, 63.5% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clock_pci_ram_clock = PERIOD TIMEGRP 
"clock_pci_ram_clock" TS_pci_clock / 3         HIGH 50%;

 6337 paths analyzed, 898 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   9.361ns.
--------------------------------------------------------------------------------
Slack:                  0.639ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/count/out_write_count_1 (FF)
  Destination:          ram/ram/page_count_11 (FF)
  Requirement:          10.000ns
  Data Path Delay:      9.203ns (Levels of Logic = 4)
  Clock Path Skew:      -0.158ns (0.538 - 0.696)
  Source Clock:         clock_ram rising at 0.000ns
  Destination Clock:    clock_ram rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/count/out_write_count_1 to ram/ram/page_count_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y2.YQ        Tcko                  0.580   fifo/fifo/count/out_write_count<0>
                                                       fifo/fifo/count/out_write_count_1
    SLICE_X7Y4.F2        net (fanout=1)        1.472   fifo/fifo/count/out_write_count<1>
    SLICE_X7Y4.COUT      Topcyf                1.195   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_lut<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X7Y5.CIN       net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X7Y5.COUT      Tbyp                  0.130   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<2>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X7Y6.CIN       net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X7Y6.XB        Tcinxb                0.296   ram/ram/read_begin_cmp_le0000
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
    SLICE_X29Y32.G2      net (fanout=3)        2.075   ram/ram/read_begin_cmp_le0000
    SLICE_X29Y32.Y       Tilo                  0.648   ram/ram/read_address_not0001
                                                       ram/ram/page_address_not0001
    SLICE_X22Y48.CE      net (fanout=17)       2.496   ram/ram/page_address_not0001
    SLICE_X22Y48.CLK     Tceck                 0.311   ram/ram/page_count<10>
                                                       ram/ram/page_count_11
    -------------------------------------------------  ---------------------------
    Total                                      9.203ns (3.160ns logic, 6.043ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------
Slack:                  0.639ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/count/out_write_count_1 (FF)
  Destination:          ram/ram/page_count_13 (FF)
  Requirement:          10.000ns
  Data Path Delay:      9.203ns (Levels of Logic = 4)
  Clock Path Skew:      -0.158ns (0.538 - 0.696)
  Source Clock:         clock_ram rising at 0.000ns
  Destination Clock:    clock_ram rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/count/out_write_count_1 to ram/ram/page_count_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y2.YQ        Tcko                  0.580   fifo/fifo/count/out_write_count<0>
                                                       fifo/fifo/count/out_write_count_1
    SLICE_X7Y4.F2        net (fanout=1)        1.472   fifo/fifo/count/out_write_count<1>
    SLICE_X7Y4.COUT      Topcyf                1.195   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_lut<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X7Y5.CIN       net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X7Y5.COUT      Tbyp                  0.130   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<2>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X7Y6.CIN       net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X7Y6.XB        Tcinxb                0.296   ram/ram/read_begin_cmp_le0000
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
    SLICE_X29Y32.G2      net (fanout=3)        2.075   ram/ram/read_begin_cmp_le0000
    SLICE_X29Y32.Y       Tilo                  0.648   ram/ram/read_address_not0001
                                                       ram/ram/page_address_not0001
    SLICE_X22Y49.CE      net (fanout=17)       2.496   ram/ram/page_address_not0001
    SLICE_X22Y49.CLK     Tceck                 0.311   ram/ram/page_count<12>
                                                       ram/ram/page_count_13
    -------------------------------------------------  ---------------------------
    Total                                      9.203ns (3.160ns logic, 6.043ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------
Slack:                  0.639ns (requirement - (data path - clock path skew + uncertainty))
  Source:               fifo/fifo/count/out_write_count_1 (FF)
  Destination:          ram/ram/page_count_12 (FF)
  Requirement:          10.000ns
  Data Path Delay:      9.203ns (Levels of Logic = 4)
  Clock Path Skew:      -0.158ns (0.538 - 0.696)
  Source Clock:         clock_ram rising at 0.000ns
  Destination Clock:    clock_ram rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: fifo/fifo/count/out_write_count_1 to ram/ram/page_count_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y2.YQ        Tcko                  0.580   fifo/fifo/count/out_write_count<0>
                                                       fifo/fifo/count/out_write_count_1
    SLICE_X7Y4.F2        net (fanout=1)        1.472   fifo/fifo/count/out_write_count<1>
    SLICE_X7Y4.COUT      Topcyf                1.195   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_lut<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<0>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X7Y5.CIN       net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<1>
    SLICE_X7Y5.COUT      Tbyp                  0.130   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<2>
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X7Y6.CIN       net (fanout=1)        0.000   ram/ram/Mcompar_read_begin_cmp_le0000_cy<3>
    SLICE_X7Y6.XB        Tcinxb                0.296   ram/ram/read_begin_cmp_le0000
                                                       ram/ram/Mcompar_read_begin_cmp_le0000_cy<4>
    SLICE_X29Y32.G2      net (fanout=3)        2.075   ram/ram/read_begin_cmp_le0000
    SLICE_X29Y32.Y       Tilo                  0.648   ram/ram/read_address_not0001
                                                       ram/ram/page_address_not0001
    SLICE_X22Y49.CE      net (fanout=17)       2.496   ram/ram/page_address_not0001
    SLICE_X22Y49.CLK     Tceck                 0.311   ram/ram/page_count<12>
                                                       ram/ram/page_count_12
    -------------------------------------------------  ---------------------------
    Total                                      9.203ns (3.160ns logic, 6.043ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 5.8 ns BEFORE COMP 
"in_pci_clock";

 810 paths analyzed, 254 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   5.996ns.
--------------------------------------------------------------------------------
Slack:                  0.004ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               io_pci_trdy (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_10 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          6.000ns
  Data Path Delay:      8.445ns (Levels of Logic = 6)
  Clock Path Delay:     2.449ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    G3.I                 Tiopi                 1.256   io_pci_trdy
                                                       io_pci_trdy
                                                       io_pci_trdy_IOBUF/IBUF
                                                       io_pci_trdy.DELAY_ADJ
                                                       ProtoComp307.ISELMUX.3
    SLICE_X1Y36.G3       net (fanout=22)       0.927   N423
    SLICE_X1Y36.Y        Tilo                  0.648   fifo/_COND_120<2>
                                                       pci/pci/initiator/out_local_done_mux0000111
    SLICE_X4Y32.F3       net (fanout=7)        0.756   pci/pci/initiator/N12
    SLICE_X4Y32.X        Tilo                  0.692   pci/pci/initiator/continue_complex
                                                       fifo/_COND_120<0>1
    SLICE_X0Y25.F1       net (fanout=32)       1.394   fifo/_COND_120<0>
    SLICE_X0Y25.X        Tilo                  0.692   fifo_read_data<10>
                                                       fifo/Mram_read_data11.SLICEM_F
    SLICE_X0Y24.G2       net (fanout=1)        0.121   fifo_read_data<10>
    SLICE_X0Y24.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad<10>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux000021181
    SLICE_X0Y24.F1       net (fanout=1)        0.450   pci/pci/ad_cbe/Mmux_out_pci_ad_mux000021181/O
    SLICE_X0Y24.CLK      Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<10>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00002144
                                                       pci/pci/ad_cbe/out_pci_ad_10
    -------------------------------------------------  ---------------------------
    Total                                      8.445ns (4.797ns logic, 3.648ns route)
                                                       (56.8% logic, 43.2% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.237   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X0Y24.CLK      net (fanout=687)      0.927   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.449ns (1.285ns logic, 1.164ns route)
                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------
Slack:                  0.016ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               io_pci_trdy (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_21 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          6.000ns
  Data Path Delay:      8.367ns (Levels of Logic = 6)
  Clock Path Delay:     2.383ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    G3.I                 Tiopi                 1.256   io_pci_trdy
                                                       io_pci_trdy
                                                       io_pci_trdy_IOBUF/IBUF
                                                       io_pci_trdy.DELAY_ADJ
                                                       ProtoComp307.ISELMUX.3
    SLICE_X1Y36.G3       net (fanout=22)       0.927   N423
    SLICE_X1Y36.Y        Tilo                  0.648   fifo/_COND_120<2>
                                                       pci/pci/initiator/out_local_done_mux0000111
    SLICE_X1Y36.F3       net (fanout=7)        0.064   pci/pci/initiator/N12
    SLICE_X1Y36.X        Tilo                  0.643   fifo/_COND_120<2>
                                                       fifo/_COND_120<2>1
    SLICE_X8Y40.F3       net (fanout=32)       2.013   fifo/_COND_120<2>
    SLICE_X8Y40.X        Tilo                  0.692   fifo_read_data<21>
                                                       fifo/Mram_read_data22.SLICEM_F
    SLICE_X8Y41.G1       net (fanout=1)        0.165   fifo_read_data<21>
    SLICE_X8Y41.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad<21>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001467
    SLICE_X8Y41.F1       net (fanout=1)        0.450   pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001467/O
    SLICE_X8Y41.CLK      Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<21>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001493
                                                       pci/pci/ad_cbe/out_pci_ad_21
    -------------------------------------------------  ---------------------------
    Total                                      8.367ns (4.748ns logic, 3.619ns route)
                                                       (56.7% logic, 43.3% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.237   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X8Y41.CLK      net (fanout=687)      0.861   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.383ns (1.285ns logic, 1.098ns route)
                                                       (53.9% logic, 46.1% route)

--------------------------------------------------------------------------------
Slack:                  0.029ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               io_pci_trdy (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_3 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          6.000ns
  Data Path Delay:      8.406ns (Levels of Logic = 6)
  Clock Path Delay:     2.435ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    G3.I                 Tiopi                 1.256   io_pci_trdy
                                                       io_pci_trdy
                                                       io_pci_trdy_IOBUF/IBUF
                                                       io_pci_trdy.DELAY_ADJ
                                                       ProtoComp307.ISELMUX.3
    SLICE_X1Y36.G3       net (fanout=22)       0.927   N423
    SLICE_X1Y36.Y        Tilo                  0.648   fifo/_COND_120<2>
                                                       pci/pci/initiator/out_local_done_mux0000111
    SLICE_X1Y36.F3       net (fanout=7)        0.064   pci/pci/initiator/N12
    SLICE_X1Y36.X        Tilo                  0.643   fifo/_COND_120<2>
                                                       fifo/_COND_120<2>1
    SLICE_X4Y29.F3       net (fanout=32)       2.158   fifo/_COND_120<2>
    SLICE_X4Y29.X        Tilo                  0.692   fifo_read_data<3>
                                                       fifo/Mram_read_data4.SLICEM_F
    SLICE_X4Y30.G1       net (fanout=1)        0.449   fifo_read_data<3>
    SLICE_X4Y30.Y        Tilo                  0.707   pci/pci/ad_cbe/out_pci_ad<3>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux000026118
    SLICE_X4Y30.F4       net (fanout=1)        0.060   pci/pci/ad_cbe/Mmux_out_pci_ad_mux000026118/O
    SLICE_X4Y30.CLK      Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<3>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux000026144
                                                       pci/pci/ad_cbe/out_pci_ad_3
    -------------------------------------------------  ---------------------------
    Total                                      8.406ns (4.748ns logic, 3.658ns route)
                                                       (56.5% logic, 43.5% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.237   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X4Y30.CLK      net (fanout=687)      0.913   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.435ns (1.285ns logic, 1.150ns route)
                                                       (52.8% logic, 47.2% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 8.8 ns BEFORE 
COMP "in_pci_clock";

 254 paths analyzed, 96 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   7.862ns.
--------------------------------------------------------------------------------
Slack:                  1.138ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_pci_gnt (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_30 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.283ns (Levels of Logic = 6)
  Clock Path Delay:     2.421ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_30
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C7.I                 Tiopi                 1.256   in_pci_gnt
                                                       in_pci_gnt
                                                       in_pci_gnt_IBUF
                                                       in_pci_gnt.DELAY_ADJ
    SLICE_X2Y52.F3       net (fanout=9)        0.992   in_pci_gnt_IBUF
    SLICE_X2Y52.X        Tilo                  0.692   pci/pci/initiator/continue_1
                                                       pci/pci/initiator/continue_11
    SLICE_X3Y37.G3       net (fanout=5)        1.627   pci/pci/initiator/continue_1
    SLICE_X3Y37.Y        Tilo                  0.648   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable13
    SLICE_X3Y37.F4       net (fanout=1)        0.044   pci/pci/initiator/ad/out_pci_a_enable13/O
    SLICE_X3Y37.X        Tilo                  0.643   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X3Y33.G1       net (fanout=2)        0.480   pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X3Y33.Y        Tilo                  0.648   pci/pci/ad_cbe/out_pci_ad<1>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000144
    SLICE_X6Y37.F1       net (fanout=32)       2.451   pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001076
    SLICE_X6Y37.CLK      Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<30>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00002483
                                                       pci/pci/ad_cbe/out_pci_ad_30
    -------------------------------------------------  ---------------------------
    Total                                     10.283ns (4.689ns logic, 5.594ns route)
                                                       (45.6% logic, 54.4% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_30
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.237   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X6Y37.CLK      net (fanout=687)      0.899   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.421ns (1.285ns logic, 1.136ns route)
                                                       (53.1% logic, 46.9% route)

--------------------------------------------------------------------------------
Slack:                  1.180ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_pci_gnt (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_24 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.194ns (Levels of Logic = 6)
  Clock Path Delay:     2.374ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_24
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C7.I                 Tiopi                 1.256   in_pci_gnt
                                                       in_pci_gnt
                                                       in_pci_gnt_IBUF
                                                       in_pci_gnt.DELAY_ADJ
    SLICE_X2Y52.F3       net (fanout=9)        0.992   in_pci_gnt_IBUF
    SLICE_X2Y52.X        Tilo                  0.692   pci/pci/initiator/continue_1
                                                       pci/pci/initiator/continue_11
    SLICE_X3Y37.G3       net (fanout=5)        1.627   pci/pci/initiator/continue_1
    SLICE_X3Y37.Y        Tilo                  0.648   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable13
    SLICE_X3Y37.F4       net (fanout=1)        0.044   pci/pci/initiator/ad/out_pci_a_enable13/O
    SLICE_X3Y37.X        Tilo                  0.643   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X3Y33.G1       net (fanout=2)        0.480   pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X3Y33.Y        Tilo                  0.648   pci/pci/ad_cbe/out_pci_ad<1>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000144
    SLICE_X4Y44.F2       net (fanout=32)       2.362   pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001076
    SLICE_X4Y44.CLK      Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<24>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001783
                                                       pci/pci/ad_cbe/out_pci_ad_24
    -------------------------------------------------  ---------------------------
    Total                                     10.194ns (4.689ns logic, 5.505ns route)
                                                       (46.0% logic, 54.0% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_24
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.237   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X4Y44.CLK      net (fanout=687)      0.852   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.374ns (1.285ns logic, 1.089ns route)
                                                       (54.1% logic, 45.9% route)

--------------------------------------------------------------------------------
Slack:                  1.181ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_pci_gnt (PAD)
  Destination:          pci/pci/ad_cbe/out_pci_ad_31 (FF)
  Destination Clock:    clock_pci rising at 0.000ns
  Requirement:          9.000ns
  Data Path Delay:      10.188ns (Levels of Logic = 6)
  Clock Path Delay:     2.369ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_pci_gnt to pci/pci/ad_cbe/out_pci_ad_31
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C7.I                 Tiopi                 1.256   in_pci_gnt
                                                       in_pci_gnt
                                                       in_pci_gnt_IBUF
                                                       in_pci_gnt.DELAY_ADJ
    SLICE_X2Y52.F3       net (fanout=9)        0.992   in_pci_gnt_IBUF
    SLICE_X2Y52.X        Tilo                  0.692   pci/pci/initiator/continue_1
                                                       pci/pci/initiator/continue_11
    SLICE_X3Y37.G3       net (fanout=5)        1.627   pci/pci/initiator/continue_1
    SLICE_X3Y37.Y        Tilo                  0.648   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable13
    SLICE_X3Y37.F4       net (fanout=1)        0.044   pci/pci/initiator/ad/out_pci_a_enable13/O
    SLICE_X3Y37.X        Tilo                  0.643   pci/pci/initiator/ad/out_pci_a_enable41
                                                       pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X3Y33.G1       net (fanout=2)        0.480   pci/pci/initiator/ad/out_pci_a_enable41
    SLICE_X3Y33.Y        Tilo                  0.648   pci/pci/ad_cbe/out_pci_ad<1>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000144
    SLICE_X6Y45.F2       net (fanout=32)       2.356   pci/pci/ad_cbe/Mmux_out_pci_ad_mux00001076
    SLICE_X6Y45.CLK      Tfck                  0.802   pci/pci/ad_cbe/out_pci_ad<31>
                                                       pci/pci/ad_cbe/Mmux_out_pci_ad_mux00002583
                                                       pci/pci/ad_cbe/out_pci_ad_31
    -------------------------------------------------  ---------------------------
    Total                                     10.188ns (4.689ns logic, 5.499ns route)
                                                       (46.0% logic, 54.0% route)

  Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_31
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.086   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.237   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.199   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X6Y45.CLK      net (fanout=687)      0.847   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.369ns (1.285ns logic, 1.084ns route)
                                                       (54.2% logic, 45.8% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP 
"in_pci_clock";

 84 paths analyzed, 42 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   9.440ns.
--------------------------------------------------------------------------------
Slack:                  0.560ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/ad_cbe/out_pci_ad_25 (FF)
  Destination:          io_pci_ad<25> (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.609ns (Levels of Logic = 1)
  Clock Path Delay:     2.831ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_25
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.296   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X7Y36.CLK      net (fanout=687)      1.058   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.831ns (1.477ns logic, 1.354ns route)
                                                       (52.2% logic, 47.8% route)

  Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_25 to io_pci_ad<25>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y36.XQ       Tcko                  0.591   pci/pci/ad_cbe/out_pci_ad<25>
                                                       pci/pci/ad_cbe/out_pci_ad_25
    C2.O1                net (fanout=2)        2.777   pci/pci/ad_cbe/out_pci_ad<25>
    C2.PAD               Tioop                 3.241   io_pci_ad<25>
                                                       io_pci_ad_25_IOBUF/OBUFT
                                                       io_pci_ad<25>
    -------------------------------------------------  ---------------------------
    Total                                      6.609ns (3.832ns logic, 2.777ns route)
                                                       (58.0% logic, 42.0% route)

--------------------------------------------------------------------------------
Slack:                  0.666ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/ad_cbe/out_pci_ad_8 (FF)
  Destination:          io_pci_ad<8> (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.488ns (Levels of Logic = 1)
  Clock Path Delay:     2.846ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.296   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X9Y30.CLK      net (fanout=687)      1.073   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.846ns (1.477ns logic, 1.369ns route)
                                                       (51.9% logic, 48.1% route)

  Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_8 to io_pci_ad<8>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X9Y30.XQ       Tcko                  0.591   pci/pci/ad_cbe/out_pci_ad<8>
                                                       pci/pci/ad_cbe/out_pci_ad_8
    N1.O1                net (fanout=2)        2.656   pci/pci/ad_cbe/out_pci_ad<8>
    N1.PAD               Tioop                 3.241   io_pci_ad<8>
                                                       io_pci_ad_8_IOBUF/OBUFT
                                                       io_pci_ad<8>
    -------------------------------------------------  ---------------------------
    Total                                      6.488ns (3.832ns logic, 2.656ns route)
                                                       (59.1% logic, 40.9% route)

--------------------------------------------------------------------------------
Slack:                  0.800ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/ad_cbe/out_pci_ad_enable (FF)
  Destination:          io_pci_ad<30> (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.313ns (Levels of Logic = 1)
  Clock Path Delay:     2.887ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_enable
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.296   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X3Y30.CLK      net (fanout=687)      1.114   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.887ns (1.477ns logic, 1.410ns route)
                                                       (51.2% logic, 48.8% route)

  Maximum Data Path: pci/pci/ad_cbe/out_pci_ad_enable to io_pci_ad<30>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y30.YQ       Tcko                  0.580   pci/pci/ad_cbe/out_pci_ad_enable
                                                       pci/pci/ad_cbe/out_pci_ad_enable
    D7.T1                net (fanout=33)       2.717   pci/pci/ad_cbe/out_pci_ad_enable
    D7.PAD               Tiotp                 3.016   io_pci_ad<30>
                                                       io_pci_ad_30_IOBUF/OBUFT
                                                       io_pci_ad<30>
    -------------------------------------------------  ---------------------------
    Total                                      6.313ns (3.596ns logic, 2.717ns route)
                                                       (57.0% logic, 43.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP 
"in_pci_clock";

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   8.743ns.
--------------------------------------------------------------------------------
Slack:                  2.257ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               pci/pci/initiator/enable (FF)
  Destination:          out_pci_req (PAD)
  Source Clock:         clock_pci rising at 0.000ns
  Requirement:          11.000ns
  Data Path Delay:      5.926ns (Levels of Logic = 1)
  Clock Path Delay:     2.817ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: in_pci_clock to pci/pci/initiator/enable
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C8.I                 Tiopi                 1.256   in_pci_clock
                                                       in_pci_clock
                                                       clock/pci/ibufg
                                                       in_pci_clock.DELAY_ADJ
    BUFGMUX_X2Y10.I0     net (fanout=4)        0.296   clock_pci1
    BUFGMUX_X2Y10.O      Tgi0o                 0.221   clock_pci_BUFG
                                                       clock_pci_BUFG
    SLICE_X5Y55.CLK      net (fanout=687)      1.044   clock_pci
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (1.477ns logic, 1.340ns route)
                                                       (52.4% logic, 47.6% route)

  Maximum Data Path: pci/pci/initiator/enable to out_pci_req
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y55.XQ       Tcko                  0.591   pci/pci/initiator/enable
                                                       pci/pci/initiator/enable
    A4.O1                net (fanout=30)       2.094   pci/pci/initiator/enable
    A4.PAD               Tioop                 3.241   out_pci_req
                                                       out_pci_req_OBUFT
                                                       out_pci_req
    -------------------------------------------------  ---------------------------
    Total                                      5.926ns (3.832ns logic, 2.094ns route)
                                                       (64.7% logic, 35.3% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE 
COMP         "in_video_clock" TIMEGRP video_rising;

 16 paths analyzed, 16 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   0.078ns.
--------------------------------------------------------------------------------
Slack:                  1.292ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_video_horizontal (PAD)
  Destination:          video/io/horizontal (FF)
  Destination Clock:    clock_video rising at 0.000ns
  Requirement:          1.370ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.265ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_video_horizontal to video/io/horizontal
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A6.ICLK1             Tiopick               2.343   in_video_horizontal
                                                       in_video_horizontal
                                                       in_video_horizontal_IBUF
                                                       in_video_horizontal.DELAY_ADJ
                                                       video/io/horizontal
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_video_clock to video/io/horizontal
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_video_clock
                                                       in_video_clock
                                                       clock/video/ibufg
                                                       in_video_clock.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=2)        0.027   clock_video1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_video_BUFG
                                                       clock_video_BUFG
    A6.ICLK1             net (fanout=272)      0.825   clock_video
    -------------------------------------------------  ---------------------------
    Total                                      2.265ns (1.413ns logic, 0.852ns route)
                                                       (62.4% logic, 37.6% route)

--------------------------------------------------------------------------------
Slack:                  1.303ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_video_data<11> (PAD)
  Destination:          video/io/out_posedge_data_11 (FF)
  Destination Clock:    clock_video rising at 0.000ns
  Requirement:          1.370ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.276ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_video_data<11> to video/io/out_posedge_data_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A12.ICLK2            Tiopick               2.343   in_video_data<11>
                                                       in_video_data<11>
                                                       in_video_data_11_IBUF
                                                       in_video_data<11>.DELAY_ADJ
                                                       video/io/out_posedge_data_11
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_video_clock to video/io/out_posedge_data_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_video_clock
                                                       in_video_clock
                                                       clock/video/ibufg
                                                       in_video_clock.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=2)        0.027   clock_video1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_video_BUFG
                                                       clock_video_BUFG
    A12.ICLK2            net (fanout=272)      0.836   clock_video
    -------------------------------------------------  ---------------------------
    Total                                      2.276ns (1.413ns logic, 0.863ns route)
                                                       (62.1% logic, 37.9% route)

--------------------------------------------------------------------------------
Slack:                  1.303ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_video_data<10> (PAD)
  Destination:          video/io/out_posedge_data_10 (FF)
  Destination Clock:    clock_video rising at 0.000ns
  Requirement:          1.370ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.276ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_video_data<10> to video/io/out_posedge_data_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B12.ICLK2            Tiopick               2.343   in_video_data<10>
                                                       in_video_data<10>
                                                       in_video_data_10_IBUF
                                                       in_video_data<10>.DELAY_ADJ
                                                       video/io/out_posedge_data_10
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_video_clock to video/io/out_posedge_data_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_video_clock
                                                       in_video_clock
                                                       clock/video/ibufg
                                                       in_video_clock.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=2)        0.027   clock_video1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_video_BUFG
                                                       clock_video_BUFG
    B12.ICLK2            net (fanout=272)      0.836   clock_video
    -------------------------------------------------  ---------------------------
    Total                                      2.276ns (1.413ns logic, 0.863ns route)
                                                       (62.1% logic, 37.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE 
COMP         "in_video_clock" TIMEGRP video_falling;

 15 paths analyzed, 15 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Offset is  -6.673ns.
--------------------------------------------------------------------------------
Slack:                  1.303ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_video_data<11> (PAD)
  Destination:          video/io/out_negedge_data_11 (FF)
  Destination Clock:    clock_video falling at 6.740ns
  Requirement:          -5.370ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.276ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_video_data<11> to video/io/out_negedge_data_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A12.ICLK1            Tiopick               2.343   in_video_data<11>
                                                       in_video_data<11>
                                                       in_video_data_11_IBUF
                                                       in_video_data<11>.DELAY_ADJ
                                                       video/io/out_negedge_data_11
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_video_clock to video/io/out_negedge_data_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_video_clock
                                                       in_video_clock
                                                       clock/video/ibufg
                                                       in_video_clock.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=2)        0.027   clock_video1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_video_BUFG
                                                       clock_video_BUFG
    A12.ICLK1            net (fanout=272)      0.836   clock_video
    -------------------------------------------------  ---------------------------
    Total                                      2.276ns (1.413ns logic, 0.863ns route)
                                                       (62.1% logic, 37.9% route)

--------------------------------------------------------------------------------
Slack:                  1.303ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_video_data<10> (PAD)
  Destination:          video/io/out_negedge_data_10 (FF)
  Destination Clock:    clock_video falling at 6.740ns
  Requirement:          -5.370ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.276ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_video_data<10> to video/io/out_negedge_data_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B12.ICLK1            Tiopick               2.343   in_video_data<10>
                                                       in_video_data<10>
                                                       in_video_data_10_IBUF
                                                       in_video_data<10>.DELAY_ADJ
                                                       video/io/out_negedge_data_10
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_video_clock to video/io/out_negedge_data_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_video_clock
                                                       in_video_clock
                                                       clock/video/ibufg
                                                       in_video_clock.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=2)        0.027   clock_video1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_video_BUFG
                                                       clock_video_BUFG
    B12.ICLK1            net (fanout=272)      0.836   clock_video
    -------------------------------------------------  ---------------------------
    Total                                      2.276ns (1.413ns logic, 0.863ns route)
                                                       (62.1% logic, 37.9% route)

--------------------------------------------------------------------------------
Slack:                  1.306ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               in_video_data<5> (PAD)
  Destination:          video/io/out_negedge_data_5 (FF)
  Destination Clock:    clock_video falling at 6.740ns
  Requirement:          -5.370ns
  Data Path Delay:      2.343ns (Levels of Logic = 0)
  Clock Path Delay:     2.279ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: in_video_data<5> to video/io/out_negedge_data_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D10.ICLK1            Tiopick               2.343   in_video_data<5>
                                                       in_video_data<5>
                                                       in_video_data_5_IBUF
                                                       in_video_data<5>.DELAY_ADJ
                                                       video/io/out_negedge_data_5
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (2.343ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: in_video_clock to video/io/out_negedge_data_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.214   in_video_clock
                                                       in_video_clock
                                                       clock/video/ibufg
                                                       in_video_clock.DELAY_ADJ
    BUFGMUX_X1Y11.I0     net (fanout=2)        0.027   clock_video1
    BUFGMUX_X1Y11.O      Tgi0o                 0.199   clock_video_BUFG
                                                       clock_video_BUFG
    D10.ICLK1            net (fanout=272)      0.839   clock_video
    -------------------------------------------------  ---------------------------
    Total                                      2.279ns (1.413ns logic, 0.866ns route)
                                                       (62.0% logic, 38.0% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_pci_clock
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_pci_clock                   |     30.000ns|     15.532ns|     28.083ns|            0|            0|        44165|         6337|
| TS_clock_pci_ram_clock        |     10.000ns|      9.361ns|          N/A|            0|            0|         6337|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock in_pci_clock
-------------+------------+------------+------------------+--------+
             |  Setup to  |  Hold to   |                  | Clock  |
Source       | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
-------------+------------+------------+------------------+--------+
in_pci_gnt   |    7.862(R)|   -1.734(R)|clock_pci         |   0.000|
in_pci_idsel |    4.664(R)|   -1.241(R)|clock_pci         |   0.000|
io_pci_ad<0> |    4.705(R)|   -1.290(R)|clock_pci         |   0.000|
io_pci_ad<1> |    4.708(R)|   -1.294(R)|clock_pci         |   0.000|
io_pci_ad<2> |    4.705(R)|   -1.290(R)|clock_pci         |   0.000|
io_pci_ad<3> |    4.708(R)|   -1.294(R)|clock_pci         |   0.000|
io_pci_ad<4> |    4.741(R)|   -1.333(R)|clock_pci         |   0.000|
io_pci_ad<5> |    4.715(R)|   -1.301(R)|clock_pci         |   0.000|
io_pci_ad<6> |    4.741(R)|   -1.333(R)|clock_pci         |   0.000|
io_pci_ad<7> |    4.715(R)|   -1.301(R)|clock_pci         |   0.000|
io_pci_ad<8> |    4.734(R)|   -1.324(R)|clock_pci         |   0.000|
io_pci_ad<9> |    4.730(R)|   -1.320(R)|clock_pci         |   0.000|
io_pci_ad<10>|    4.734(R)|   -1.324(R)|clock_pci         |   0.000|
io_pci_ad<11>|    4.707(R)|   -1.292(R)|clock_pci         |   0.000|
io_pci_ad<12>|    4.710(R)|   -1.296(R)|clock_pci         |   0.000|
io_pci_ad<13>|    4.722(R)|   -1.310(R)|clock_pci         |   0.000|
io_pci_ad<14>|    4.710(R)|   -1.296(R)|clock_pci         |   0.000|
io_pci_ad<15>|    4.728(R)|   -1.318(R)|clock_pci         |   0.000|
io_pci_ad<16>|    4.752(R)|   -1.346(R)|clock_pci         |   0.000|
io_pci_ad<17>|    4.748(R)|   -1.341(R)|clock_pci         |   0.000|
io_pci_ad<18>|    4.682(R)|   -1.263(R)|clock_pci         |   0.000|
io_pci_ad<19>|    4.692(R)|   -1.275(R)|clock_pci         |   0.000|
io_pci_ad<20>|    4.730(R)|   -1.319(R)|clock_pci         |   0.000|
io_pci_ad<21>|    4.730(R)|   -1.319(R)|clock_pci         |   0.000|
io_pci_ad<22>|    4.682(R)|   -1.263(R)|clock_pci         |   0.000|
io_pci_ad<23>|    4.692(R)|   -1.275(R)|clock_pci         |   0.000|
io_pci_ad<24>|    4.764(R)|   -1.359(R)|clock_pci         |   0.000|
io_pci_ad<25>|    4.675(R)|   -1.255(R)|clock_pci         |   0.000|
io_pci_ad<26>|    4.661(R)|   -1.239(R)|clock_pci         |   0.000|
io_pci_ad<27>|    4.641(R)|   -1.214(R)|clock_pci         |   0.000|
io_pci_ad<28>|    4.765(R)|   -1.361(R)|clock_pci         |   0.000|
io_pci_ad<29>|    4.641(R)|   -1.214(R)|clock_pci         |   0.000|
io_pci_ad<30>|    4.765(R)|   -1.361(R)|clock_pci         |   0.000|
io_pci_ad<31>|    4.752(R)|   -1.345(R)|clock_pci         |   0.000|
io_pci_cbe<0>|    4.803(R)|   -1.320(R)|clock_pci         |   0.000|
io_pci_cbe<1>|    4.723(R)|   -1.292(R)|clock_pci         |   0.000|
io_pci_cbe<2>|    4.731(R)|   -1.321(R)|clock_pci         |   0.000|
io_pci_cbe<3>|    4.984(R)|   -1.255(R)|clock_pci         |   0.000|
io_pci_devsel|    5.606(R)|   -0.312(R)|clock_pci         |   0.000|
io_pci_frame |    5.502(R)|   -0.345(R)|clock_pci         |   0.000|
io_pci_irdy  |    5.412(R)|   -0.226(R)|clock_pci         |   0.000|
io_pci_stop  |    5.921(R)|   -0.398(R)|clock_pci         |   0.000|
io_pci_trdy  |    5.996(R)|   -0.464(R)|clock_pci         |   0.000|
-------------+------------+------------+------------------+--------+

Setup/Hold to clock in_video_clock
-------------------+------------+------------+------------------+--------+
                   |  Setup to  |  Hold to   |                  | Clock  |
Source             | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
-------------------+------------+------------+------------------+--------+
in_video_data<0>   |    0.030(R)|    1.473(R)|clock_video       |   0.000|
                   |   -6.710(F)|    8.213(F)|clock_video       |   6.740|
in_video_data<1>   |   -0.026(R)|    1.538(R)|clock_video       |   0.000|
                   |   -6.766(F)|    8.278(F)|clock_video       |   6.740|
in_video_data<2>   |    0.041(R)|    1.459(R)|clock_video       |   0.000|
                   |   -6.699(F)|    8.199(F)|clock_video       |   6.740|
in_video_data<3>   |    0.058(R)|    1.439(R)|clock_video       |   0.000|
                   |   -6.682(F)|    8.179(F)|clock_video       |   6.740|
in_video_data<4>   |    0.058(R)|    1.439(R)|clock_video       |   0.000|
                   |   -6.682(F)|    8.179(F)|clock_video       |   6.740|
in_video_data<5>   |    0.064(R)|    1.433(R)|clock_video       |   0.000|
                   |   -6.676(F)|    8.173(F)|clock_video       |   6.740|
in_video_data<6>   |    0.041(R)|    1.460(R)|clock_video       |   0.000|
                   |   -6.699(F)|    8.200(F)|clock_video       |   6.740|
in_video_data<7>   |   -0.026(R)|    1.538(R)|clock_video       |   0.000|
                   |   -6.766(F)|    8.278(F)|clock_video       |   6.740|
in_video_data<8>   |    0.062(R)|    1.434(R)|clock_video       |   0.000|
                   |   -6.678(F)|    8.174(F)|clock_video       |   6.740|
in_video_data<9>   |    0.062(R)|    1.434(R)|clock_video       |   0.000|
                   |   -6.678(F)|    8.174(F)|clock_video       |   6.740|
in_video_data<10>  |    0.067(R)|    1.428(R)|clock_video       |   0.000|
                   |   -6.673(F)|    8.168(F)|clock_video       |   6.740|
in_video_data<11>  |    0.067(R)|    1.428(R)|clock_video       |   0.000|
                   |   -6.673(F)|    8.168(F)|clock_video       |   6.740|
in_video_data<12>  |    0.030(R)|    1.473(R)|clock_video       |   0.000|
                   |   -6.710(F)|    8.213(F)|clock_video       |   6.740|
in_video_data<13>  |    0.050(R)|    1.448(R)|clock_video       |   0.000|
                   |   -6.690(F)|    8.188(F)|clock_video       |   6.740|
in_video_data<14>  |    0.051(R)|    1.447(R)|clock_video       |   0.000|
                   |   -6.689(F)|    8.187(F)|clock_video       |   6.740|
in_video_horizontal|    0.078(R)|    1.416(R)|clock_video       |   0.000|
-------------------+------------+------------+------------------+--------+

Clock in_pci_clock to Pad
-------------+------------+------------------+--------+
             | clk (edge) |                  | Clock  |
Destination  |   to PAD   |Internal Clock(s) | Phase  |
-------------+------------+------------------+--------+
io_pci_ad<0> |    8.802(R)|clock_pci         |   0.000|
io_pci_ad<1> |    8.632(R)|clock_pci         |   0.000|
io_pci_ad<2> |    9.141(R)|clock_pci         |   0.000|
io_pci_ad<3> |    9.141(R)|clock_pci         |   0.000|
io_pci_ad<4> |    8.312(R)|clock_pci         |   0.000|
io_pci_ad<5> |    9.131(R)|clock_pci         |   0.000|
io_pci_ad<6> |    8.091(R)|clock_pci         |   0.000|
io_pci_ad<7> |    8.901(R)|clock_pci         |   0.000|
io_pci_ad<8> |    9.334(R)|clock_pci         |   0.000|
io_pci_ad<9> |    8.817(R)|clock_pci         |   0.000|
io_pci_ad<10>|    8.146(R)|clock_pci         |   0.000|
io_pci_ad<11>|    7.899(R)|clock_pci         |   0.000|
io_pci_ad<12>|    8.807(R)|clock_pci         |   0.000|
io_pci_ad<13>|    8.410(R)|clock_pci         |   0.000|
io_pci_ad<14>|    8.051(R)|clock_pci         |   0.000|
io_pci_ad<15>|    8.517(R)|clock_pci         |   0.000|
io_pci_ad<16>|    8.330(R)|clock_pci         |   0.000|
io_pci_ad<17>|    8.476(R)|clock_pci         |   0.000|
io_pci_ad<18>|    8.664(R)|clock_pci         |   0.000|
io_pci_ad<19>|    8.334(R)|clock_pci         |   0.000|
io_pci_ad<20>|    8.303(R)|clock_pci         |   0.000|
io_pci_ad<21>|    8.798(R)|clock_pci         |   0.000|
io_pci_ad<22>|    8.552(R)|clock_pci         |   0.000|
io_pci_ad<23>|    8.820(R)|clock_pci         |   0.000|
io_pci_ad<24>|    8.684(R)|clock_pci         |   0.000|
io_pci_ad<25>|    9.440(R)|clock_pci         |   0.000|
io_pci_ad<26>|    8.978(R)|clock_pci         |   0.000|
io_pci_ad<27>|    8.958(R)|clock_pci         |   0.000|
io_pci_ad<28>|    8.692(R)|clock_pci         |   0.000|
io_pci_ad<29>|    8.823(R)|clock_pci         |   0.000|
io_pci_ad<30>|    9.200(R)|clock_pci         |   0.000|
io_pci_ad<31>|    8.672(R)|clock_pci         |   0.000|
io_pci_cbe<0>|    8.208(R)|clock_pci         |   0.000|
io_pci_cbe<1>|    8.161(R)|clock_pci         |   0.000|
io_pci_cbe<2>|    7.800(R)|clock_pci         |   0.000|
io_pci_cbe<3>|    8.345(R)|clock_pci         |   0.000|
io_pci_devsel|    7.348(R)|clock_pci         |   0.000|
io_pci_frame |    7.422(R)|clock_pci         |   0.000|
io_pci_irdy  |    7.929(R)|clock_pci         |   0.000|
io_pci_stop  |    8.408(R)|clock_pci         |   0.000|
io_pci_trdy  |    8.507(R)|clock_pci         |   0.000|
out_pci_par  |    7.159(R)|clock_pci         |   0.000|
out_pci_req  |    8.743(R)|clock_pci         |   0.000|
-------------+------------+------------------+--------+

Clock to Setup on destination clock in_pci_clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_pci_clock   |   15.532|         |    2.812|         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock in_video_clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_video_clock |    9.107|    3.939|         |         |
---------------+---------+---------+---------+---------+

TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 5.8 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 5.770; Ideal Clock Offset To Actual Clock 0.011; 
-------------+------------+------------+---------+---------+-------------+
             |            |            |  Setup  |  Hold   |Source Offset|
Source       |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------+------------+------------+---------+---------+-------------+
in_pci_idsel |    4.664(R)|   -1.241(R)|    1.336|    1.041|        0.148|
io_pci_ad<0> |    4.705(R)|   -1.290(R)|    1.295|    1.090|        0.102|
io_pci_ad<1> |    4.708(R)|   -1.294(R)|    1.292|    1.094|        0.099|
io_pci_ad<2> |    4.705(R)|   -1.290(R)|    1.295|    1.090|        0.102|
io_pci_ad<3> |    4.708(R)|   -1.294(R)|    1.292|    1.094|        0.099|
io_pci_ad<4> |    4.741(R)|   -1.333(R)|    1.259|    1.133|        0.063|
io_pci_ad<5> |    4.715(R)|   -1.301(R)|    1.285|    1.101|        0.092|
io_pci_ad<6> |    4.741(R)|   -1.333(R)|    1.259|    1.133|        0.063|
io_pci_ad<7> |    4.715(R)|   -1.301(R)|    1.285|    1.101|        0.092|
io_pci_ad<8> |    4.734(R)|   -1.324(R)|    1.266|    1.124|        0.071|
io_pci_ad<9> |    4.730(R)|   -1.320(R)|    1.270|    1.120|        0.075|
io_pci_ad<10>|    4.734(R)|   -1.324(R)|    1.266|    1.124|        0.071|
io_pci_ad<11>|    4.707(R)|   -1.292(R)|    1.293|    1.092|        0.100|
io_pci_ad<12>|    4.710(R)|   -1.296(R)|    1.290|    1.096|        0.097|
io_pci_ad<13>|    4.722(R)|   -1.310(R)|    1.278|    1.110|        0.084|
io_pci_ad<14>|    4.710(R)|   -1.296(R)|    1.290|    1.096|        0.097|
io_pci_ad<15>|    4.728(R)|   -1.318(R)|    1.272|    1.118|        0.077|
io_pci_ad<16>|    4.752(R)|   -1.346(R)|    1.248|    1.146|        0.051|
io_pci_ad<17>|    4.748(R)|   -1.341(R)|    1.252|    1.141|        0.055|
io_pci_ad<18>|    4.682(R)|   -1.263(R)|    1.318|    1.063|        0.128|
io_pci_ad<19>|    4.692(R)|   -1.275(R)|    1.308|    1.075|        0.117|
io_pci_ad<20>|    4.730(R)|   -1.319(R)|    1.270|    1.119|        0.076|
io_pci_ad<21>|    4.730(R)|   -1.319(R)|    1.270|    1.119|        0.076|
io_pci_ad<22>|    4.682(R)|   -1.263(R)|    1.318|    1.063|        0.128|
io_pci_ad<23>|    4.692(R)|   -1.275(R)|    1.308|    1.075|        0.117|
io_pci_ad<24>|    4.764(R)|   -1.359(R)|    1.236|    1.159|        0.038|
io_pci_ad<25>|    4.675(R)|   -1.255(R)|    1.325|    1.055|        0.135|
io_pci_ad<26>|    4.661(R)|   -1.239(R)|    1.339|    1.039|        0.150|
io_pci_ad<27>|    4.641(R)|   -1.214(R)|    1.359|    1.014|        0.172|
io_pci_ad<28>|    4.765(R)|   -1.361(R)|    1.235|    1.161|        0.037|
io_pci_ad<29>|    4.641(R)|   -1.214(R)|    1.359|    1.014|        0.172|
io_pci_ad<30>|    4.765(R)|   -1.361(R)|    1.235|    1.161|        0.037|
io_pci_ad<31>|    4.752(R)|   -1.345(R)|    1.248|    1.145|        0.051|
io_pci_cbe<0>|    4.803(R)|   -1.320(R)|    1.197|    1.120|        0.038|
io_pci_cbe<1>|    4.723(R)|   -1.292(R)|    1.277|    1.092|        0.092|
io_pci_cbe<2>|    4.731(R)|   -1.321(R)|    1.269|    1.121|        0.074|
io_pci_cbe<3>|    4.984(R)|   -1.255(R)|    1.016|    1.055|       -0.019|
io_pci_devsel|    5.606(R)|   -0.312(R)|    0.394|    0.112|        0.141|
io_pci_frame |    5.502(R)|   -0.345(R)|    0.498|    0.145|        0.177|
io_pci_irdy  |    5.412(R)|   -0.226(R)|    0.588|    0.026|        0.281|
io_pci_stop  |    5.921(R)|   -0.398(R)|    0.079|    0.198|       -0.060|
io_pci_trdy  |    5.996(R)|   -0.464(R)|    0.004|    0.264|       -0.130|
-------------+------------+------------+---------+---------+-------------+
Worst Case   |            |            |         |         |             |
Summary      |       5.996|      -0.226|    0.004|    0.026|             |
-------------+------------+------------+---------+---------+-------------+

TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 8.8 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 6.128; Ideal Clock Offset To Actual Clock 0.198; 
------------+------------+------------+---------+---------+-------------+
            |            |            |  Setup  |  Hold   |Source Offset|
Source      |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
------------+------------+------------+---------+---------+-------------+
in_pci_gnt  |    7.862(R)|   -1.734(R)|    1.138|    1.534|       -0.198|
------------+------------+------------+---------+---------+-------------+
Worst Case  |            |            |         |         |             |
Summary     |       7.862|      -1.734|    1.138|    1.534|             |
------------+------------+------------+---------+---------+-------------+

TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE COMP         "in_video_clock" TIMEGRP video_rising;
Worst Case Data Window 1.616; Ideal Clock Offset To Actual Clock 0.020; 
-------------------+------------+------------+---------+---------+-------------+
                   |            |            |  Setup  |  Hold   |Source Offset|
Source             |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
in_video_data<0>   |    0.030(R)|    1.473(R)|    1.340|    1.397|       -0.028|
in_video_data<1>   |   -0.026(R)|    1.538(R)|    1.396|    1.332|        0.032|
in_video_data<2>   |    0.041(R)|    1.459(R)|    1.329|    1.411|       -0.041|
in_video_data<3>   |    0.058(R)|    1.439(R)|    1.312|    1.431|       -0.060|
in_video_data<4>   |    0.058(R)|    1.439(R)|    1.312|    1.431|       -0.060|
in_video_data<5>   |    0.064(R)|    1.433(R)|    1.306|    1.437|       -0.066|
in_video_data<6>   |    0.041(R)|    1.460(R)|    1.329|    1.410|       -0.040|
in_video_data<7>   |   -0.026(R)|    1.538(R)|    1.396|    1.332|        0.032|
in_video_data<8>   |    0.062(R)|    1.434(R)|    1.308|    1.436|       -0.064|
in_video_data<9>   |    0.062(R)|    1.434(R)|    1.308|    1.436|       -0.064|
in_video_data<10>  |    0.067(R)|    1.428(R)|    1.303|    1.442|       -0.070|
in_video_data<11>  |    0.067(R)|    1.428(R)|    1.303|    1.442|       -0.070|
in_video_data<12>  |    0.030(R)|    1.473(R)|    1.340|    1.397|       -0.028|
in_video_data<13>  |    0.050(R)|    1.448(R)|    1.320|    1.422|       -0.051|
in_video_data<14>  |    0.051(R)|    1.447(R)|    1.319|    1.423|       -0.052|
in_video_horizontal|    0.078(R)|    1.416(R)|    1.292|    1.454|       -0.081|
-------------------+------------+------------+---------+---------+-------------+
Worst Case         |            |            |         |         |             |
Summary            |       0.078|       1.538|    1.292|    1.332|             |
-------------------+------------+------------+---------+---------+-------------+

TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE COMP         "in_video_clock" TIMEGRP video_falling;
Worst Case Data Window 1.605; Ideal Clock Offset To Actual Clock 0.015; 
-----------------+------------+------------+---------+---------+-------------+
                 |            |            |  Setup  |  Hold   |Source Offset|
Source           |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-----------------+------------+------------+---------+---------+-------------+
in_video_data<0> |   -6.710(F)|    8.213(F)|    1.340|    1.397|       -0.028|
in_video_data<1> |   -6.766(F)|    8.278(F)|    1.396|    1.332|        0.032|
in_video_data<2> |   -6.699(F)|    8.199(F)|    1.329|    1.411|       -0.041|
in_video_data<3> |   -6.682(F)|    8.179(F)|    1.312|    1.431|       -0.060|
in_video_data<4> |   -6.682(F)|    8.179(F)|    1.312|    1.431|       -0.060|
in_video_data<5> |   -6.676(F)|    8.173(F)|    1.306|    1.437|       -0.066|
in_video_data<6> |   -6.699(F)|    8.200(F)|    1.329|    1.410|       -0.040|
in_video_data<7> |   -6.766(F)|    8.278(F)|    1.396|    1.332|        0.032|
in_video_data<8> |   -6.678(F)|    8.174(F)|    1.308|    1.436|       -0.064|
in_video_data<9> |   -6.678(F)|    8.174(F)|    1.308|    1.436|       -0.064|
in_video_data<10>|   -6.673(F)|    8.168(F)|    1.303|    1.442|       -0.070|
in_video_data<11>|   -6.673(F)|    8.168(F)|    1.303|    1.442|       -0.070|
in_video_data<12>|   -6.710(F)|    8.213(F)|    1.340|    1.397|       -0.028|
in_video_data<13>|   -6.690(F)|    8.188(F)|    1.320|    1.422|       -0.051|
in_video_data<14>|   -6.689(F)|    8.187(F)|    1.319|    1.423|       -0.052|
-----------------+------------+------------+---------+---------+-------------+
Worst Case       |            |            |         |         |             |
Summary          |      -6.673|       8.278|    1.303|    1.332|             |
-----------------+------------+------------+---------+---------+-------------+

TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP "in_pci_clock";
Bus Skew: 2.281 ns; 
-----------------------------------------------+-------------+-------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+-------------+
io_pci_ad<0>                                   |        8.802|        1.643|
io_pci_ad<1>                                   |        8.632|        1.473|
io_pci_ad<2>                                   |        9.141|        1.982|
io_pci_ad<3>                                   |        9.141|        1.982|
io_pci_ad<4>                                   |        8.312|        1.153|
io_pci_ad<5>                                   |        9.131|        1.972|
io_pci_ad<6>                                   |        8.091|        0.932|
io_pci_ad<7>                                   |        8.901|        1.742|
io_pci_ad<8>                                   |        9.334|        2.175|
io_pci_ad<9>                                   |        8.817|        1.658|
io_pci_ad<10>                                  |        8.146|        0.987|
io_pci_ad<11>                                  |        7.899|        0.740|
io_pci_ad<12>                                  |        8.807|        1.648|
io_pci_ad<13>                                  |        8.410|        1.251|
io_pci_ad<14>                                  |        8.051|        0.892|
io_pci_ad<15>                                  |        8.517|        1.358|
io_pci_ad<16>                                  |        8.330|        1.171|
io_pci_ad<17>                                  |        8.476|        1.317|
io_pci_ad<18>                                  |        8.664|        1.505|
io_pci_ad<19>                                  |        8.334|        1.175|
io_pci_ad<20>                                  |        8.303|        1.144|
io_pci_ad<21>                                  |        8.798|        1.639|
io_pci_ad<22>                                  |        8.552|        1.393|
io_pci_ad<23>                                  |        8.820|        1.661|
io_pci_ad<24>                                  |        8.684|        1.525|
io_pci_ad<25>                                  |        9.440|        2.281|
io_pci_ad<26>                                  |        8.978|        1.819|
io_pci_ad<27>                                  |        8.958|        1.799|
io_pci_ad<28>                                  |        8.692|        1.533|
io_pci_ad<29>                                  |        8.823|        1.664|
io_pci_ad<30>                                  |        9.200|        2.041|
io_pci_ad<31>                                  |        8.672|        1.513|
io_pci_cbe<0>                                  |        8.208|        1.049|
io_pci_cbe<1>                                  |        8.161|        1.002|
io_pci_cbe<2>                                  |        7.800|        0.641|
io_pci_cbe<3>                                  |        8.345|        1.186|
io_pci_devsel                                  |        7.348|        0.189|
io_pci_frame                                   |        7.422|        0.263|
io_pci_irdy                                    |        7.929|        0.770|
io_pci_stop                                    |        8.408|        1.249|
io_pci_trdy                                    |        8.507|        1.348|
out_pci_par                                    |        7.159|        0.000|
-----------------------------------------------+-------------+-------------+

TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP "in_pci_clock";
Bus Skew: 0.000 ns; 
-----------------------------------------------+-------------+-------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+-------------+
out_pci_req                                    |        8.743|        0.000|
-----------------------------------------------+-------------+-------------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 101028 paths, 0 nets, and 10833 connections

Design statistics:
   Minimum period:  15.532ns{1}   (Maximum frequency:  64.383MHz)
   Minimum input required time before clock:   7.862ns
   Minimum output required time after clock:   9.440ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed SAT 20 DEC 18:10:44 2008 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 150 MB