PCI パリティ出力回路のバグを修正しました。
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Release 9.1.03i Trace
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
K:\ISE\bin\nt\trce.exe -ise E:/RTL/_/PV.ise -intstyle ise -e 3 -s 4 -xml PV
PV.ncd -o PV.twr PV.pcf -ucf E:/RTL/Code/UCF/PV.ucf
Design file: pv.ncd
Physical constraint file: pv.pcf
Device,package,speed: xc3s200a,ft256,-4 (PRODUCTION 1.38 2007-08-28)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_pci_clock = PERIOD TIMEGRP "pci_clock" 30 ns HIGH 50%;
32168 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 19.923ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_video_clock = PERIOD TIMEGRP "video_clock" 13.48 ns HIGH
50%;
39107 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 10.660ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clock_pci_rx_clock = PERIOD TIMEGRP "clock_pci_rx_clock"
TS_pci_clock * 2 HIGH 50%;
13131 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 12.827ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clock_pci_ram_clock = PERIOD TIMEGRP
"clock_pci_ram_clock" TS_pci_clock / 3 HIGH 50%;
5730 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 9.537ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 6 ns BEFORE COMP
"in_pci_clock";
284 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 5.882ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 9 ns BEFORE COMP
"in_pci_clock";
7 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 5.447ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP
"in_pci_clock";
84 items analyzed, 0 timing errors detected.
Minimum allowable offset is 9.618ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP
"in_pci_clock";
2 items analyzed, 0 timing errors detected.
Minimum allowable offset is 6.679ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE
COMP "in_video_clock" TIMEGRP video_rising;
16 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Offset is -0.071ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE
COMP "in_video_clock" TIMEGRP video_falling;
15 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Offset is -6.822ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "ram_in" OFFSET = IN 8 ns VALID 16 ns BEFORE COMP
"in_pci_clock";
32 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 1.535ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "ram_out" OFFSET = OUT 15 ns AFTER COMP
"in_pci_clock";
80 items analyzed, 0 timing errors detected.
Minimum allowable offset is 14.158ns.
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock in_pci_clock
---------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
---------------+------------+------------+------------------+--------+
in_pci_gnt | 5.447(R)| -0.692(R)|clock_pci | 0.000|
in_pci_idsel | 1.964(R)| -0.338(R)|clock_pci | 0.000|
io_pci_ad<0> | 1.981(R)| -0.357(R)|clock_pci | 0.000|
io_pci_ad<1> | 1.984(R)| -0.361(R)|clock_pci | 0.000|
io_pci_ad<2> | 1.981(R)| -0.357(R)|clock_pci | 0.000|
io_pci_ad<3> | 1.984(R)| -0.361(R)|clock_pci | 0.000|
io_pci_ad<4> | 2.017(R)| -0.400(R)|clock_pci | 0.000|
io_pci_ad<5> | 1.991(R)| -0.368(R)|clock_pci | 0.000|
io_pci_ad<6> | 2.017(R)| -0.400(R)|clock_pci | 0.000|
io_pci_ad<7> | 1.991(R)| -0.368(R)|clock_pci | 0.000|
io_pci_ad<8> | 2.010(R)| -0.391(R)|clock_pci | 0.000|
io_pci_ad<9> | 2.006(R)| -0.387(R)|clock_pci | 0.000|
io_pci_ad<10> | 2.010(R)| -0.391(R)|clock_pci | 0.000|
io_pci_ad<11> | 1.983(R)| -0.359(R)|clock_pci | 0.000|
io_pci_ad<12> | 1.986(R)| -0.363(R)|clock_pci | 0.000|
io_pci_ad<13> | 1.998(R)| -0.377(R)|clock_pci | 0.000|
io_pci_ad<14> | 1.986(R)| -0.363(R)|clock_pci | 0.000|
io_pci_ad<15> | 2.004(R)| -0.385(R)|clock_pci | 0.000|
io_pci_ad<16> | 2.028(R)| -0.413(R)|clock_pci | 0.000|
io_pci_ad<17> | 2.024(R)| -0.408(R)|clock_pci | 0.000|
io_pci_ad<18> | 1.977(R)| -0.352(R)|clock_pci | 0.000|
io_pci_ad<19> | 1.983(R)| -0.360(R)|clock_pci | 0.000|
io_pci_ad<20> | 2.012(R)| -0.394(R)|clock_pci | 0.000|
io_pci_ad<21> | 2.012(R)| -0.394(R)|clock_pci | 0.000|
io_pci_ad<22> | 1.977(R)| -0.352(R)|clock_pci | 0.000|
io_pci_ad<23> | 1.983(R)| -0.360(R)|clock_pci | 0.000|
io_pci_ad<24> | 2.040(R)| -0.426(R)|clock_pci | 0.000|
io_pci_ad<25> | 1.973(R)| -0.348(R)|clock_pci | 0.000|
io_pci_ad<26> | 1.932(R)| -0.300(R)|clock_pci | 0.000|
io_pci_ad<27> | 1.925(R)| -0.291(R)|clock_pci | 0.000|
io_pci_ad<28> | 2.041(R)| -0.428(R)|clock_pci | 0.000|
io_pci_ad<29> | 1.925(R)| -0.291(R)|clock_pci | 0.000|
io_pci_ad<30> | 2.041(R)| -0.428(R)|clock_pci | 0.000|
io_pci_ad<31> | 2.017(R)| -0.400(R)|clock_pci | 0.000|
io_pci_cbe<0> | 2.006(R)| -0.387(R)|clock_pci | 0.000|
io_pci_cbe<1> | 1.983(R)| -0.359(R)|clock_pci | 0.000|
io_pci_cbe<2> | 2.007(R)| -0.388(R)|clock_pci | 0.000|
io_pci_cbe<3> | 1.973(R)| -0.348(R)|clock_pci | 0.000|
io_pci_devsel | 3.618(R)| -0.053(R)|clock_pci | 0.000|
io_pci_frame | 3.649(R)| -0.156(R)|clock_pci | 0.000|
io_pci_irdy | 2.245(R)| -0.057(R)|clock_pci | 0.000|
io_pci_stop | 4.036(R)| -0.414(R)|clock_pci | 0.000|
io_pci_trdy | 5.882(R)| -0.503(R)|clock_pci | 0.000|
io_ram_data<0> | 1.459(R)| 1.202(R)|clock_ram | 0.000|
io_ram_data<1> | 1.506(R)| 1.146(R)|clock_ram | 0.000|
io_ram_data<2> | 1.506(R)| 1.146(R)|clock_ram | 0.000|
io_ram_data<3> | 1.494(R)| 1.160(R)|clock_ram | 0.000|
io_ram_data<4> | 1.477(R)| 1.181(R)|clock_ram | 0.000|
io_ram_data<5> | 1.436(R)| 1.228(R)|clock_ram | 0.000|
io_ram_data<6> | 1.436(R)| 1.228(R)|clock_ram | 0.000|
io_ram_data<7> | 1.445(R)| 1.217(R)|clock_ram | 0.000|
io_ram_data<8> | 1.520(R)| 1.129(R)|clock_ram | 0.000|
io_ram_data<9> | 1.522(R)| 1.127(R)|clock_ram | 0.000|
io_ram_data<10>| 1.517(R)| 1.133(R)|clock_ram | 0.000|
io_ram_data<11>| 1.522(R)| 1.127(R)|clock_ram | 0.000|
io_ram_data<12>| 1.522(R)| 1.127(R)|clock_ram | 0.000|
io_ram_data<13>| 1.451(R)| 1.211(R)|clock_ram | 0.000|
io_ram_data<14>| 1.451(R)| 1.211(R)|clock_ram | 0.000|
io_ram_data<15>| 1.459(R)| 1.202(R)|clock_ram | 0.000|
io_ram_data<16>| 1.445(R)| 1.217(R)|clock_ram | 0.000|
io_ram_data<17>| 1.504(R)| 1.148(R)|clock_ram | 0.000|
io_ram_data<18>| 1.504(R)| 1.148(R)|clock_ram | 0.000|
io_ram_data<19>| 1.484(R)| 1.171(R)|clock_ram | 0.000|
io_ram_data<20>| 1.484(R)| 1.171(R)|clock_ram | 0.000|
io_ram_data<21>| 1.471(R)| 1.187(R)|clock_ram | 0.000|
io_ram_data<22>| 1.471(R)| 1.187(R)|clock_ram | 0.000|
io_ram_data<23>| 1.509(R)| 1.142(R)|clock_ram | 0.000|
io_ram_data<24>| 1.514(R)| 1.136(R)|clock_ram | 0.000|
io_ram_data<25>| 1.535(R)| 1.112(R)|clock_ram | 0.000|
io_ram_data<26>| 1.535(R)| 1.112(R)|clock_ram | 0.000|
io_ram_data<27>| 1.504(R)| 1.149(R)|clock_ram | 0.000|
io_ram_data<28>| 1.504(R)| 1.149(R)|clock_ram | 0.000|
io_ram_data<29>| 1.467(R)| 1.192(R)|clock_ram | 0.000|
io_ram_data<30>| 1.491(R)| 1.163(R)|clock_ram | 0.000|
io_ram_data<31>| 1.491(R)| 1.163(R)|clock_ram | 0.000|
---------------+------------+------------+------------------+--------+
Setup/Hold to clock in_video_clock
-------------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-------------------+------------+------------+------------------+--------+
in_video_data<0> | -0.123(R)| 1.664(R)|clock_video | 0.000|
| -6.863(F)| 8.404(F)|clock_video | 6.740|
in_video_data<1> | -0.151(R)| 1.697(R)|clock_video | 0.000|
| -6.891(F)| 8.437(F)|clock_video | 6.740|
in_video_data<2> | -0.104(R)| 1.641(R)|clock_video | 0.000|
| -6.844(F)| 8.381(F)|clock_video | 6.740|
in_video_data<3> | -0.091(R)| 1.626(R)|clock_video | 0.000|
| -6.831(F)| 8.366(F)|clock_video | 6.740|
in_video_data<4> | -0.091(R)| 1.626(R)|clock_video | 0.000|
| -6.831(F)| 8.366(F)|clock_video | 6.740|
in_video_data<5> | -0.085(R)| 1.620(R)|clock_video | 0.000|
| -6.825(F)| 8.360(F)|clock_video | 6.740|
in_video_data<6> | -0.108(R)| 1.647(R)|clock_video | 0.000|
| -6.848(F)| 8.387(F)|clock_video | 6.740|
in_video_data<7> | -0.151(R)| 1.697(R)|clock_video | 0.000|
| -6.891(F)| 8.437(F)|clock_video | 6.740|
in_video_data<8> | -0.087(R)| 1.621(R)|clock_video | 0.000|
| -6.827(F)| 8.361(F)|clock_video | 6.740|
in_video_data<9> | -0.087(R)| 1.621(R)|clock_video | 0.000|
| -6.827(F)| 8.361(F)|clock_video | 6.740|
in_video_data<10> | -0.082(R)| 1.615(R)|clock_video | 0.000|
| -6.822(F)| 8.355(F)|clock_video | 6.740|
in_video_data<11> | -0.082(R)| 1.615(R)|clock_video | 0.000|
| -6.822(F)| 8.355(F)|clock_video | 6.740|
in_video_data<12> | -0.123(R)| 1.664(R)|clock_video | 0.000|
| -6.863(F)| 8.404(F)|clock_video | 6.740|
in_video_data<13> | -0.096(R)| 1.632(R)|clock_video | 0.000|
| -6.836(F)| 8.372(F)|clock_video | 6.740|
in_video_data<14> | -0.098(R)| 1.634(R)|clock_video | 0.000|
| -6.838(F)| 8.374(F)|clock_video | 6.740|
in_video_horizontal| -0.071(R)| 1.603(R)|clock_video | 0.000|
-------------------+------------+------------+------------------+--------+
Clock in_pci_clock to Pad
--------------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
--------------------+------------+------------------+--------+
io_pci_ad<0> | 8.580(R)|clock_pci | 0.000|
io_pci_ad<1> | 8.603(R)|clock_pci | 0.000|
io_pci_ad<2> | 8.993(R)|clock_pci | 0.000|
io_pci_ad<3> | 9.272(R)|clock_pci | 0.000|
io_pci_ad<4> | 8.383(R)|clock_pci | 0.000|
io_pci_ad<5> | 9.272(R)|clock_pci | 0.000|
io_pci_ad<6> | 8.034(R)|clock_pci | 0.000|
io_pci_ad<7> | 8.728(R)|clock_pci | 0.000|
io_pci_ad<8> | 8.871(R)|clock_pci | 0.000|
io_pci_ad<9> | 8.662(R)|clock_pci | 0.000|
io_pci_ad<10> | 8.997(R)|clock_pci | 0.000|
io_pci_ad<11> | 8.374(R)|clock_pci | 0.000|
io_pci_ad<12> | 7.467(R)|clock_pci | 0.000|
io_pci_ad<13> | 8.662(R)|clock_pci | 0.000|
io_pci_ad<14> | 7.958(R)|clock_pci | 0.000|
io_pci_ad<15> | 7.795(R)|clock_pci | 0.000|
io_pci_ad<16> | 8.604(R)|clock_pci | 0.000|
io_pci_ad<17> | 8.873(R)|clock_pci | 0.000|
io_pci_ad<18> | 8.597(R)|clock_pci | 0.000|
io_pci_ad<19> | 8.840(R)|clock_pci | 0.000|
io_pci_ad<20> | 8.318(R)|clock_pci | 0.000|
io_pci_ad<21> | 8.165(R)|clock_pci | 0.000|
io_pci_ad<22> | 8.580(R)|clock_pci | 0.000|
io_pci_ad<23> | 8.318(R)|clock_pci | 0.000|
io_pci_ad<24> | 8.883(R)|clock_pci | 0.000|
io_pci_ad<25> | 8.597(R)|clock_pci | 0.000|
io_pci_ad<26> | 8.284(R)|clock_pci | 0.000|
io_pci_ad<27> | 8.863(R)|clock_pci | 0.000|
io_pci_ad<28> | 9.155(R)|clock_pci | 0.000|
io_pci_ad<29> | 8.585(R)|clock_pci | 0.000|
io_pci_ad<30> | 9.132(R)|clock_pci | 0.000|
io_pci_ad<31> | 8.875(R)|clock_pci | 0.000|
io_pci_cbe<0> | 7.844(R)|clock_pci | 0.000|
io_pci_cbe<1> | 7.219(R)|clock_pci | 0.000|
io_pci_cbe<2> | 7.755(R)|clock_pci | 0.000|
io_pci_cbe<3> | 9.618(R)|clock_pci | 0.000|
io_pci_devsel | 6.858(R)|clock_pci | 0.000|
io_pci_frame | 8.069(R)|clock_pci | 0.000|
io_pci_irdy | 7.408(R)|clock_pci | 0.000|
io_pci_stop | 8.153(R)|clock_pci | 0.000|
io_pci_trdy | 7.884(R)|clock_pci | 0.000|
io_ram_data<0> | 10.925(R)|clock_ram | 0.000|
io_ram_data<1> | 11.265(R)|clock_ram | 0.000|
io_ram_data<2> | 11.010(R)|clock_ram | 0.000|
io_ram_data<3> | 10.656(R)|clock_ram | 0.000|
io_ram_data<4> | 10.622(R)|clock_ram | 0.000|
io_ram_data<5> | 10.042(R)|clock_ram | 0.000|
io_ram_data<6> | 10.272(R)|clock_ram | 0.000|
io_ram_data<7> | 9.515(R)|clock_ram | 0.000|
io_ram_data<8> | 11.602(R)|clock_ram | 0.000|
io_ram_data<9> | 11.204(R)|clock_ram | 0.000|
io_ram_data<10> | 11.487(R)|clock_ram | 0.000|
io_ram_data<11> | 11.072(R)|clock_ram | 0.000|
io_ram_data<12> | 12.173(R)|clock_ram | 0.000|
io_ram_data<13> | 11.337(R)|clock_ram | 0.000|
io_ram_data<14> | 10.656(R)|clock_ram | 0.000|
io_ram_data<15> | 11.068(R)|clock_ram | 0.000|
io_ram_data<16> | 9.760(R)|clock_ram | 0.000|
io_ram_data<17> | 10.539(R)|clock_ram | 0.000|
io_ram_data<18> | 10.009(R)|clock_ram | 0.000|
io_ram_data<19> | 10.579(R)|clock_ram | 0.000|
io_ram_data<20> | 10.592(R)|clock_ram | 0.000|
io_ram_data<21> | 10.850(R)|clock_ram | 0.000|
io_ram_data<22> | 10.861(R)|clock_ram | 0.000|
io_ram_data<23> | 10.992(R)|clock_ram | 0.000|
io_ram_data<24> | 14.158(R)|clock_ram | 0.000|
io_ram_data<25> | 13.615(R)|clock_ram | 0.000|
io_ram_data<26> | 13.889(R)|clock_ram | 0.000|
io_ram_data<27> | 13.322(R)|clock_ram | 0.000|
io_ram_data<28> | 13.879(R)|clock_ram | 0.000|
io_ram_data<29> | 12.821(R)|clock_ram | 0.000|
io_ram_data<30> | 12.468(R)|clock_ram | 0.000|
io_ram_data<31> | 11.999(R)|clock_ram | 0.000|
out_pci_par | 6.944(R)|clock_pci | 0.000|
out_pci_req | 6.679(R)|clock_pci | 0.000|
out_ram_address<0> | 8.640(R)|clock_ram | 0.000|
out_ram_address<1> | 8.611(R)|clock_ram | 0.000|
out_ram_address<2> | 8.622(R)|clock_ram | 0.000|
out_ram_address<3> | 8.694(R)|clock_ram | 0.000|
out_ram_address<4> | 8.636(R)|clock_ram | 0.000|
out_ram_address<5> | 8.636(R)|clock_ram | 0.000|
out_ram_address<6> | 8.584(R)|clock_ram | 0.000|
out_ram_address<7> | 8.613(R)|clock_ram | 0.000|
out_ram_address<8> | 8.600(R)|clock_ram | 0.000|
out_ram_address<9> | 8.607(R)|clock_ram | 0.000|
out_ram_address<10> | 8.611(R)|clock_ram | 0.000|
out_ram_bank<0> | 8.655(R)|clock_ram | 0.000|
out_ram_bank<1> | 8.661(R)|clock_ram | 0.000|
out_ram_col_address | 8.713(R)|clock_ram | 0.000|
out_ram_row_address | 8.713(R)|clock_ram | 0.000|
out_ram_write_enable| 8.643(R)|clock_ram | 0.000|
--------------------+------------+------------------+--------+
Clock to Setup on destination clock in_pci_clock
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_pci_clock | 13.911| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock in_video_clock
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_video_clock | 10.660| 3.439| | 2.671|
---------------+---------+---------+---------+---------+
TIMEGRP "pci_in_7" OFFSET = IN 6 ns VALID 6 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 5.829; Ideal Clock Offset To Actual Clock -0.033;
-------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
-------------+------------+------------+---------+---------+-------------+
in_pci_idsel | 1.964(R)| -0.338(R)| 4.036| 0.338| 1.849|
io_pci_ad<0> | 1.981(R)| -0.357(R)| 4.019| 0.357| 1.831|
io_pci_ad<1> | 1.984(R)| -0.361(R)| 4.016| 0.361| 1.828|
io_pci_ad<2> | 1.981(R)| -0.357(R)| 4.019| 0.357| 1.831|
io_pci_ad<3> | 1.984(R)| -0.361(R)| 4.016| 0.361| 1.828|
io_pci_ad<4> | 2.017(R)| -0.400(R)| 3.983| 0.400| 1.792|
io_pci_ad<5> | 1.991(R)| -0.368(R)| 4.009| 0.368| 1.821|
io_pci_ad<6> | 2.017(R)| -0.400(R)| 3.983| 0.400| 1.792|
io_pci_ad<7> | 1.991(R)| -0.368(R)| 4.009| 0.368| 1.821|
io_pci_ad<8> | 2.010(R)| -0.391(R)| 3.990| 0.391| 1.800|
io_pci_ad<9> | 2.006(R)| -0.387(R)| 3.994| 0.387| 1.804|
io_pci_ad<10>| 2.010(R)| -0.391(R)| 3.990| 0.391| 1.800|
io_pci_ad<11>| 1.983(R)| -0.359(R)| 4.017| 0.359| 1.829|
io_pci_ad<12>| 1.986(R)| -0.363(R)| 4.014| 0.363| 1.826|
io_pci_ad<13>| 1.998(R)| -0.377(R)| 4.002| 0.377| 1.813|
io_pci_ad<14>| 1.986(R)| -0.363(R)| 4.014| 0.363| 1.826|
io_pci_ad<15>| 2.004(R)| -0.385(R)| 3.996| 0.385| 1.806|
io_pci_ad<16>| 2.028(R)| -0.413(R)| 3.972| 0.413| 1.780|
io_pci_ad<17>| 2.024(R)| -0.408(R)| 3.976| 0.408| 1.784|
io_pci_ad<18>| 1.977(R)| -0.352(R)| 4.023| 0.352| 1.836|
io_pci_ad<19>| 1.983(R)| -0.360(R)| 4.017| 0.360| 1.829|
io_pci_ad<20>| 2.012(R)| -0.394(R)| 3.988| 0.394| 1.797|
io_pci_ad<21>| 2.012(R)| -0.394(R)| 3.988| 0.394| 1.797|
io_pci_ad<22>| 1.977(R)| -0.352(R)| 4.023| 0.352| 1.836|
io_pci_ad<23>| 1.983(R)| -0.360(R)| 4.017| 0.360| 1.829|
io_pci_ad<24>| 2.040(R)| -0.426(R)| 3.960| 0.426| 1.767|
io_pci_ad<25>| 1.973(R)| -0.348(R)| 4.027| 0.348| 1.840|
io_pci_ad<26>| 1.932(R)| -0.300(R)| 4.068| 0.300| 1.884|
io_pci_ad<27>| 1.925(R)| -0.291(R)| 4.075| 0.291| 1.892|
io_pci_ad<28>| 2.041(R)| -0.428(R)| 3.959| 0.428| 1.766|
io_pci_ad<29>| 1.925(R)| -0.291(R)| 4.075| 0.291| 1.892|
io_pci_ad<30>| 2.041(R)| -0.428(R)| 3.959| 0.428| 1.766|
io_pci_ad<31>| 2.017(R)| -0.400(R)| 3.983| 0.400| 1.792|
io_pci_cbe<0>| 2.006(R)| -0.387(R)| 3.994| 0.387| 1.804|
io_pci_cbe<1>| 1.983(R)| -0.359(R)| 4.017| 0.359| 1.829|
io_pci_cbe<2>| 2.007(R)| -0.388(R)| 3.993| 0.388| 1.803|
io_pci_cbe<3>| 1.973(R)| -0.348(R)| 4.027| 0.348| 1.840|
io_pci_devsel| 3.618(R)| -0.053(R)| 2.382| 0.053| 1.165|
io_pci_frame | 3.649(R)| -0.156(R)| 2.351| 0.156| 1.098|
io_pci_irdy | 2.245(R)| -0.057(R)| 3.755| 0.057| 1.849|
io_pci_stop | 4.036(R)| -0.414(R)| 1.964| 0.414| 0.775|
io_pci_trdy | 5.882(R)| -0.503(R)| 0.118| 0.503| -0.193|
-------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 5.882| -0.053| 0.118| 0.053| |
-------------+------------+------------+---------+---------+-------------+
TIMEGRP "pci_in_10" OFFSET = IN 9 ns VALID 9 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 4.755; Ideal Clock Offset To Actual Clock -1.430;
------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
------------+------------+------------+---------+---------+-------------+
in_pci_gnt | 5.447(R)| -0.692(R)| 3.553| 0.692| 1.430|
------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 5.447| -0.692| 3.553| 0.692| |
------------+------------+------------+---------+---------+-------------+
TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_rising;
Worst Case Data Window 1.626; Ideal Clock Offset To Actual Clock -0.134;
-------------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
-------------------+------------+------------+---------+---------+-------------+
in_video_data<0> | -0.123(R)| 1.664(R)| 1.493| 1.206| 0.144|
in_video_data<1> | -0.151(R)| 1.697(R)| 1.521| 1.173| 0.174|
in_video_data<2> | -0.104(R)| 1.641(R)| 1.474| 1.229| 0.122|
in_video_data<3> | -0.091(R)| 1.626(R)| 1.461| 1.244| 0.109|
in_video_data<4> | -0.091(R)| 1.626(R)| 1.461| 1.244| 0.109|
in_video_data<5> | -0.085(R)| 1.620(R)| 1.455| 1.250| 0.103|
in_video_data<6> | -0.108(R)| 1.647(R)| 1.478| 1.223| 0.127|
in_video_data<7> | -0.151(R)| 1.697(R)| 1.521| 1.173| 0.174|
in_video_data<8> | -0.087(R)| 1.621(R)| 1.457| 1.249| 0.104|
in_video_data<9> | -0.087(R)| 1.621(R)| 1.457| 1.249| 0.104|
in_video_data<10> | -0.082(R)| 1.615(R)| 1.452| 1.255| 0.099|
in_video_data<11> | -0.082(R)| 1.615(R)| 1.452| 1.255| 0.099|
in_video_data<12> | -0.123(R)| 1.664(R)| 1.493| 1.206| 0.144|
in_video_data<13> | -0.096(R)| 1.632(R)| 1.466| 1.238| 0.114|
in_video_data<14> | -0.098(R)| 1.634(R)| 1.468| 1.236| 0.116|
in_video_horizontal| -0.071(R)| 1.603(R)| 1.441| 1.267| 0.087|
-------------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | -0.071| 1.697| 1.441| 1.173| |
-------------------+------------+------------+---------+---------+-------------+
TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_falling;
Worst Case Data Window 1.615; Ideal Clock Offset To Actual Clock -0.139;
-----------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
-----------------+------------+------------+---------+---------+-------------+
in_video_data<0> | -6.863(F)| 8.404(F)| 1.493| 1.206| 0.144|
in_video_data<1> | -6.891(F)| 8.437(F)| 1.521| 1.173| 0.174|
in_video_data<2> | -6.844(F)| 8.381(F)| 1.474| 1.229| 0.122|
in_video_data<3> | -6.831(F)| 8.366(F)| 1.461| 1.244| 0.109|
in_video_data<4> | -6.831(F)| 8.366(F)| 1.461| 1.244| 0.109|
in_video_data<5> | -6.825(F)| 8.360(F)| 1.455| 1.250| 0.103|
in_video_data<6> | -6.848(F)| 8.387(F)| 1.478| 1.223| 0.127|
in_video_data<7> | -6.891(F)| 8.437(F)| 1.521| 1.173| 0.174|
in_video_data<8> | -6.827(F)| 8.361(F)| 1.457| 1.249| 0.104|
in_video_data<9> | -6.827(F)| 8.361(F)| 1.457| 1.249| 0.104|
in_video_data<10>| -6.822(F)| 8.355(F)| 1.452| 1.255| 0.099|
in_video_data<11>| -6.822(F)| 8.355(F)| 1.452| 1.255| 0.099|
in_video_data<12>| -6.863(F)| 8.404(F)| 1.493| 1.206| 0.144|
in_video_data<13>| -6.836(F)| 8.372(F)| 1.466| 1.238| 0.114|
in_video_data<14>| -6.838(F)| 8.374(F)| 1.468| 1.236| 0.116|
-----------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | -6.822| 8.437| 1.452| 1.173| |
-----------------+------------+------------+---------+---------+-------------+
TIMEGRP "ram_in" OFFSET = IN 8 ns VALID 16 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 2.763; Ideal Clock Offset To Actual Clock 0.154;
---------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
---------------+------------+------------+---------+---------+-------------+
io_ram_data<0> | 1.459(R)| 1.202(R)| 6.541| 6.798| -0.128|
io_ram_data<1> | 1.506(R)| 1.146(R)| 6.494| 6.854| -0.180|
io_ram_data<2> | 1.506(R)| 1.146(R)| 6.494| 6.854| -0.180|
io_ram_data<3> | 1.494(R)| 1.160(R)| 6.506| 6.840| -0.167|
io_ram_data<4> | 1.477(R)| 1.181(R)| 6.523| 6.819| -0.148|
io_ram_data<5> | 1.436(R)| 1.228(R)| 6.564| 6.772| -0.104|
io_ram_data<6> | 1.436(R)| 1.228(R)| 6.564| 6.772| -0.104|
io_ram_data<7> | 1.445(R)| 1.217(R)| 6.555| 6.783| -0.114|
io_ram_data<8> | 1.520(R)| 1.129(R)| 6.480| 6.871| -0.196|
io_ram_data<9> | 1.522(R)| 1.127(R)| 6.478| 6.873| -0.198|
io_ram_data<10>| 1.517(R)| 1.133(R)| 6.483| 6.867| -0.192|
io_ram_data<11>| 1.522(R)| 1.127(R)| 6.478| 6.873| -0.198|
io_ram_data<12>| 1.522(R)| 1.127(R)| 6.478| 6.873| -0.198|
io_ram_data<13>| 1.451(R)| 1.211(R)| 6.549| 6.789| -0.120|
io_ram_data<14>| 1.451(R)| 1.211(R)| 6.549| 6.789| -0.120|
io_ram_data<15>| 1.459(R)| 1.202(R)| 6.541| 6.798| -0.128|
io_ram_data<16>| 1.445(R)| 1.217(R)| 6.555| 6.783| -0.114|
io_ram_data<17>| 1.504(R)| 1.148(R)| 6.496| 6.852| -0.178|
io_ram_data<18>| 1.504(R)| 1.148(R)| 6.496| 6.852| -0.178|
io_ram_data<19>| 1.484(R)| 1.171(R)| 6.516| 6.829| -0.156|
io_ram_data<20>| 1.484(R)| 1.171(R)| 6.516| 6.829| -0.156|
io_ram_data<21>| 1.471(R)| 1.187(R)| 6.529| 6.813| -0.142|
io_ram_data<22>| 1.471(R)| 1.187(R)| 6.529| 6.813| -0.142|
io_ram_data<23>| 1.509(R)| 1.142(R)| 6.491| 6.858| -0.184|
io_ram_data<24>| 1.514(R)| 1.136(R)| 6.486| 6.864| -0.189|
io_ram_data<25>| 1.535(R)| 1.112(R)| 6.465| 6.888| -0.212|
io_ram_data<26>| 1.535(R)| 1.112(R)| 6.465| 6.888| -0.212|
io_ram_data<27>| 1.504(R)| 1.149(R)| 6.496| 6.851| -0.177|
io_ram_data<28>| 1.504(R)| 1.149(R)| 6.496| 6.851| -0.177|
io_ram_data<29>| 1.467(R)| 1.192(R)| 6.533| 6.808| -0.137|
io_ram_data<30>| 1.491(R)| 1.163(R)| 6.509| 6.837| -0.164|
io_ram_data<31>| 1.491(R)| 1.163(R)| 6.509| 6.837| -0.164|
---------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 1.535| 1.228| 6.465| 6.772| |
---------------+------------+------------+---------+---------+-------------+
TIMEGRP "pci_out_11" OFFSET = OUT 10 ns AFTER COMP "in_pci_clock";
Largest slack: 3.142 ns; Smallest slack: 0.382 ns; Relative Skew: 2.760 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
io_pci_ad<0> | 1.420| 1.722|
io_pci_ad<1> | 1.397| 1.745|
io_pci_ad<2> | 1.007| 2.135|
io_pci_ad<3> | 0.728| 2.414|
io_pci_ad<4> | 1.617| 1.525|
io_pci_ad<5> | 0.728| 2.414|
io_pci_ad<6> | 1.966| 1.176|
io_pci_ad<7> | 1.272| 1.870|
io_pci_ad<8> | 1.129| 2.013|
io_pci_ad<9> | 1.338| 1.804|
io_pci_ad<10> | 1.003| 2.139|
io_pci_ad<11> | 1.626| 1.516|
io_pci_ad<12> | 2.533| 0.609|
io_pci_ad<13> | 1.338| 1.804|
io_pci_ad<14> | 2.042| 1.100|
io_pci_ad<15> | 2.205| 0.937|
io_pci_ad<16> | 1.396| 1.746|
io_pci_ad<17> | 1.127| 2.015|
io_pci_ad<18> | 1.403| 1.739|
io_pci_ad<19> | 1.160| 1.982|
io_pci_ad<20> | 1.682| 1.460|
io_pci_ad<21> | 1.835| 1.307|
io_pci_ad<22> | 1.420| 1.722|
io_pci_ad<23> | 1.682| 1.460|
io_pci_ad<24> | 1.117| 2.025|
io_pci_ad<25> | 1.403| 1.739|
io_pci_ad<26> | 1.716| 1.426|
io_pci_ad<27> | 1.137| 2.005|
io_pci_ad<28> | 0.845| 2.297|
io_pci_ad<29> | 1.415| 1.727|
io_pci_ad<30> | 0.868| 2.274|
io_pci_ad<31> | 1.125| 2.017|
io_pci_cbe<0> | 2.156| 0.986|
io_pci_cbe<1> | 2.781| 0.361|
io_pci_cbe<2> | 2.245| 0.897|
io_pci_cbe<3> | 0.382| 2.760|
io_pci_devsel | 3.142| 0.000|
io_pci_frame | 1.931| 1.211|
io_pci_irdy | 2.592| 0.550|
io_pci_stop | 1.847| 1.295|
io_pci_trdy | 2.116| 1.026|
out_pci_par | 3.056| 0.086|
-----------------------------------------------+-------------+-------------+
TIMEGRP "pci_out_12" OFFSET = OUT 11 ns AFTER COMP "in_pci_clock";
Largest slack: 4.321 ns; Smallest slack: 4.321 ns; Relative Skew: 0.000 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
out_pci_req | 4.321| 0.000|
-----------------------------------------------+-------------+-------------+
TIMEGRP "ram_out" OFFSET = OUT 15 ns AFTER COMP "in_pci_clock";
Largest slack: 6.416 ns; Smallest slack: 0.842 ns; Relative Skew: 5.574 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
io_ram_data<0> | 4.075| 2.341|
io_ram_data<1> | 3.735| 2.681|
io_ram_data<2> | 3.990| 2.426|
io_ram_data<3> | 4.344| 2.072|
io_ram_data<4> | 4.378| 2.038|
io_ram_data<5> | 4.958| 1.458|
io_ram_data<6> | 4.728| 1.688|
io_ram_data<7> | 5.485| 0.931|
io_ram_data<8> | 3.398| 3.018|
io_ram_data<9> | 3.796| 2.620|
io_ram_data<10> | 3.513| 2.903|
io_ram_data<11> | 3.928| 2.488|
io_ram_data<12> | 2.827| 3.589|
io_ram_data<13> | 3.663| 2.753|
io_ram_data<14> | 4.344| 2.072|
io_ram_data<15> | 3.932| 2.484|
io_ram_data<16> | 5.240| 1.176|
io_ram_data<17> | 4.461| 1.955|
io_ram_data<18> | 4.991| 1.425|
io_ram_data<19> | 4.421| 1.995|
io_ram_data<20> | 4.408| 2.008|
io_ram_data<21> | 4.150| 2.266|
io_ram_data<22> | 4.139| 2.277|
io_ram_data<23> | 4.008| 2.408|
io_ram_data<24> | 0.842| 5.574|
io_ram_data<25> | 1.385| 5.031|
io_ram_data<26> | 1.111| 5.305|
io_ram_data<27> | 1.678| 4.738|
io_ram_data<28> | 1.121| 5.295|
io_ram_data<29> | 2.179| 4.237|
io_ram_data<30> | 2.532| 3.884|
io_ram_data<31> | 3.001| 3.415|
out_ram_address<0> | 6.360| 0.056|
out_ram_address<1> | 6.389| 0.027|
out_ram_address<2> | 6.378| 0.038|
out_ram_address<3> | 6.306| 0.110|
out_ram_address<4> | 6.364| 0.052|
out_ram_address<5> | 6.364| 0.052|
out_ram_address<6> | 6.416| 0.000|
out_ram_address<7> | 6.387| 0.029|
out_ram_address<8> | 6.400| 0.016|
out_ram_address<9> | 6.393| 0.023|
out_ram_address<10> | 6.389| 0.027|
out_ram_bank<0> | 6.345| 0.071|
out_ram_bank<1> | 6.339| 0.077|
out_ram_col_address | 6.287| 0.129|
out_ram_row_address | 6.287| 0.129|
out_ram_write_enable | 6.357| 0.059|
-----------------------------------------------+-------------+-------------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 90656 paths, 0 nets, and 10486 connections
Design statistics:
Minimum period: 19.923ns (Maximum frequency: 50.193MHz)
Minimum input required time before clock: 5.882ns
Minimum output required time after clock: 14.158ns
Analysis completed FRI 5 OCT 15:56:19 2007
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 169 MB