PV3 リリース番号: 02
--------------------------------------------------------------------------------
Release 9.2.04i Trace
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
D:\Xilinx92i\bin\nt\trce.exe -ise E:/RTL/_/PV.ise -intstyle ise -e 3 -s 4 -xml
PV PV.ncd -o PV.twr PV.pcf -ucf E:/RTL/Code/UCF/PV.ucf
Design file: pv.ncd
Physical constraint file: pv.pcf
Device,package,speed: xc3s500e,ft256,-4 (PRODUCTION 1.27 2007-10-19)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_pci_clock = PERIOD TIMEGRP "pci_clock" 30 ns HIGH 50%;
60169 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 17.793ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_video_clock = PERIOD TIMEGRP "video_clock" 13.48 ns HIGH
50%;
49396 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 9.875ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clock_pci_ram_clock = PERIOD TIMEGRP
"clock_pci_ram_clock" TS_pci_clock / 3 HIGH 50%;
6303 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 9.656ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_in_7" OFFSET = IN 5.62 ns VALID 5.62 ns BEFORE
COMP "in_pci_clock";
646 items analyzed, 1 timing error detected. (1 setup error, 0 hold errors)
Minimum allowable offset is 5.622ns.
--------------------------------------------------------------------------------
Slack: -0.002ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: io_pci_trdy (PAD)
Destination: pci/pci/ad_cbe/out_pci_ad_0 (FF)
Destination Clock: clock_pci rising at 0.000ns
Requirement: 5.620ns
Data Path Delay: 8.428ns (Levels of Logic = 6)
Clock Path Delay: 2.806ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Data Path: io_pci_trdy to pci/pci/ad_cbe/out_pci_ad_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J2.I Tiopi 1.716 io_pci_trdy
io_pci_trdy
io_pci_trdy_IOBUF/IBUF
ProtoComp305.ISELMUX.3
SLICE_X3Y51.G3 net (fanout=21) 0.833 N5979
SLICE_X3Y51.Y Tilo 0.704 fifo/_COND_120<1>
pci/pci/initiator/out_local_done_mux0000112
SLICE_X3Y52.F4 net (fanout=7) 0.315 pci/pci/initiator/N121
SLICE_X3Y52.X Tilo 0.704 fifo/read_index_0_2
fifo/_COND_120<2>1
SLICE_X2Y40.F3 net (fanout=32) 0.911 fifo/_COND_120<2>
SLICE_X2Y40.X Tilo 0.759 fifo_read_data<0>
fifo/inst_Mram_mem4.SLICEM_F
SLICE_X0Y32.G3 net (fanout=1) 0.812 fifo_read_data<0>
SLICE_X0Y32.Y Tilo 0.759 pci/pci/ad_cbe/out_pci_ad<0>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000132
SLICE_X0Y32.F4 net (fanout=1) 0.023 pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000132/O
SLICE_X0Y32.CLK Tfck 0.892 pci/pci/ad_cbe/out_pci_ad<0>
pci/pci/ad_cbe/Mmux_out_pci_ad_mux0000154
pci/pci/ad_cbe/out_pci_ad_0
------------------------------------------------- ---------------------------
Total 8.428ns (5.534ns logic, 2.894ns route)
(65.7% logic, 34.3% route)
Minimum Clock Path: in_pci_clock to pci/pci/ad_cbe/out_pci_ad_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 1.456 in_pci_clock
in_pci_clock
clock/pci/ibufg
BUFGMUX_X2Y11.I0 net (fanout=5) 0.037 clock_pci1
BUFGMUX_X2Y11.O Tgi0o 1.166 clock_pci_BUFG
clock_pci_BUFG
SLICE_X0Y32.CLK net (fanout=674) 0.147 clock_pci
------------------------------------------------- ---------------------------
Total 2.806ns (2.622ns logic, 0.184ns route)
(93.4% logic, 6.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_in_10" OFFSET = IN 8.62 ns VALID 8.62 ns BEFORE
COMP "in_pci_clock";
150 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum allowable offset is 7.463ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_out_11" OFFSET = OUT 9.62 ns AFTER COMP
"in_pci_clock";
84 items analyzed, 0 timing errors detected.
Minimum allowable offset is 9.578ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "pci_out_12" OFFSET = OUT 10.62 ns AFTER COMP
"in_pci_clock";
1 item analyzed, 0 timing errors detected.
Minimum allowable offset is 9.735ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE
COMP "in_video_clock" TIMEGRP video_rising;
11 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Offset is -0.262ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE
COMP "in_video_clock" TIMEGRP video_falling;
10 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Offset is -7.002ns.
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock in_pci_clock
-------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-------------+------------+------------+------------------+--------+
in_pci_gnt | 7.463(R)| -1.228(R)|clock_pci | 0.000|
in_pci_idsel | 3.942(R)| -0.493(R)|clock_pci | 0.000|
io_pci_ad<0> | 3.938(R)| -0.489(R)|clock_pci | 0.000|
io_pci_ad<1> | 3.949(R)| -0.502(R)|clock_pci | 0.000|
io_pci_ad<2> | 3.938(R)| -0.489(R)|clock_pci | 0.000|
io_pci_ad<3> | 3.949(R)| -0.502(R)|clock_pci | 0.000|
io_pci_ad<4> | 3.942(R)| -0.493(R)|clock_pci | 0.000|
io_pci_ad<5> | 3.963(R)| -0.518(R)|clock_pci | 0.000|
io_pci_ad<6> | 3.942(R)| -0.493(R)|clock_pci | 0.000|
io_pci_ad<7> | 3.964(R)| -0.519(R)|clock_pci | 0.000|
io_pci_ad<8> | 3.964(R)| -0.519(R)|clock_pci | 0.000|
io_pci_ad<9> | 3.948(R)| -0.500(R)|clock_pci | 0.000|
io_pci_ad<10>| 3.953(R)| -0.506(R)|clock_pci | 0.000|
io_pci_ad<11>| 3.967(R)| -0.522(R)|clock_pci | 0.000|
io_pci_ad<12>| 3.954(R)| -0.507(R)|clock_pci | 0.000|
io_pci_ad<13>| 3.958(R)| -0.512(R)|clock_pci | 0.000|
io_pci_ad<14>| 3.965(R)| -0.521(R)|clock_pci | 0.000|
io_pci_ad<15>| 3.963(R)| -0.518(R)|clock_pci | 0.000|
io_pci_ad<16>| 3.948(R)| -0.501(R)|clock_pci | 0.000|
io_pci_ad<17>| 3.951(R)| -0.504(R)|clock_pci | 0.000|
io_pci_ad<18>| 3.948(R)| -0.501(R)|clock_pci | 0.000|
io_pci_ad<19>| 3.940(R)| -0.491(R)|clock_pci | 0.000|
io_pci_ad<20>| 3.964(R)| -0.519(R)|clock_pci | 0.000|
io_pci_ad<21>| 3.944(R)| -0.496(R)|clock_pci | 0.000|
io_pci_ad<22>| 3.964(R)| -0.519(R)|clock_pci | 0.000|
io_pci_ad<23>| 3.944(R)| -0.496(R)|clock_pci | 0.000|
io_pci_ad<24>| 3.937(R)| -0.488(R)|clock_pci | 0.000|
io_pci_ad<25>| 3.937(R)| -0.488(R)|clock_pci | 0.000|
io_pci_ad<26>| 3.938(R)| -0.489(R)|clock_pci | 0.000|
io_pci_ad<27>| 3.958(R)| -0.512(R)|clock_pci | 0.000|
io_pci_ad<28>| 3.963(R)| -0.518(R)|clock_pci | 0.000|
io_pci_ad<29>| 3.963(R)| -0.518(R)|clock_pci | 0.000|
io_pci_ad<30>| 3.969(R)| -0.525(R)|clock_pci | 0.000|
io_pci_ad<31>| 3.958(R)| -0.512(R)|clock_pci | 0.000|
io_pci_cbe<0>| 5.098(R)| -0.500(R)|clock_pci | 0.000|
io_pci_cbe<1>| 4.652(R)| -0.521(R)|clock_pci | 0.000|
io_pci_cbe<2>| 4.368(R)| -0.515(R)|clock_pci | 0.000|
io_pci_cbe<3>| 5.364(R)| -0.491(R)|clock_pci | 0.000|
io_pci_devsel| 5.047(R)| -0.117(R)|clock_pci | 0.000|
io_pci_frame | 5.020(R)| -0.360(R)|clock_pci | 0.000|
io_pci_irdy | 4.758(R)| -0.209(R)|clock_pci | 0.000|
io_pci_stop | 5.265(R)| -0.197(R)|clock_pci | 0.000|
io_pci_trdy | 5.622(R)| -0.415(R)|clock_pci | 0.000|
-------------+------------+------------+------------------+--------+
Setup/Hold to clock in_video_clock
-------------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-------------------+------------+------------+------------------+--------+
in_video_data<0> | -0.286(R)| 2.177(R)|clock_video | 0.000|
| -7.026(F)| 8.917(F)|clock_video | 6.740|
in_video_data<1> | -0.262(R)| 2.148(R)|clock_video | 0.000|
| -7.002(F)| 8.888(F)|clock_video | 6.740|
in_video_data<2> | -0.299(R)| 2.192(R)|clock_video | 0.000|
| -7.039(F)| 8.932(F)|clock_video | 6.740|
in_video_data<3> | -0.299(R)| 2.192(R)|clock_video | 0.000|
| -7.039(F)| 8.932(F)|clock_video | 6.740|
in_video_data<4> | -0.282(R)| 2.172(R)|clock_video | 0.000|
| -7.022(F)| 8.912(F)|clock_video | 6.740|
in_video_data<5> | -0.282(R)| 2.172(R)|clock_video | 0.000|
| -7.022(F)| 8.912(F)|clock_video | 6.740|
in_video_data<6> | -0.276(R)| 2.165(R)|clock_video | 0.000|
| -7.016(F)| 8.905(F)|clock_video | 6.740|
in_video_data<7> | -0.281(R)| 2.171(R)|clock_video | 0.000|
| -7.021(F)| 8.911(F)|clock_video | 6.740|
in_video_data<8> | -0.285(R)| 2.176(R)|clock_video | 0.000|
| -7.025(F)| 8.916(F)|clock_video | 6.740|
in_video_data<9> | -0.285(R)| 2.176(R)|clock_video | 0.000|
| -7.025(F)| 8.916(F)|clock_video | 6.740|
in_video_horizontal| -0.281(R)| 2.171(R)|clock_video | 0.000|
-------------------+------------+------------+------------------+--------+
Clock in_pci_clock to Pad
-------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
-------------+------------+------------------+--------+
io_pci_ad<0> | 8.979(R)|clock_pci | 0.000|
io_pci_ad<1> | 8.915(R)|clock_pci | 0.000|
io_pci_ad<2> | 9.157(R)|clock_pci | 0.000|
io_pci_ad<3> | 8.792(R)|clock_pci | 0.000|
io_pci_ad<4> | 9.230(R)|clock_pci | 0.000|
io_pci_ad<5> | 9.066(R)|clock_pci | 0.000|
io_pci_ad<6> | 9.168(R)|clock_pci | 0.000|
io_pci_ad<7> | 9.422(R)|clock_pci | 0.000|
io_pci_ad<8> | 9.089(R)|clock_pci | 0.000|
io_pci_ad<9> | 9.446(R)|clock_pci | 0.000|
io_pci_ad<10>| 8.815(R)|clock_pci | 0.000|
io_pci_ad<11>| 9.317(R)|clock_pci | 0.000|
io_pci_ad<12>| 8.578(R)|clock_pci | 0.000|
io_pci_ad<13>| 9.059(R)|clock_pci | 0.000|
io_pci_ad<14>| 8.476(R)|clock_pci | 0.000|
io_pci_ad<15>| 9.345(R)|clock_pci | 0.000|
io_pci_ad<16>| 8.703(R)|clock_pci | 0.000|
io_pci_ad<17>| 8.911(R)|clock_pci | 0.000|
io_pci_ad<18>| 8.975(R)|clock_pci | 0.000|
io_pci_ad<19>| 8.853(R)|clock_pci | 0.000|
io_pci_ad<20>| 9.229(R)|clock_pci | 0.000|
io_pci_ad<21>| 8.842(R)|clock_pci | 0.000|
io_pci_ad<22>| 9.099(R)|clock_pci | 0.000|
io_pci_ad<23>| 9.022(R)|clock_pci | 0.000|
io_pci_ad<24>| 9.269(R)|clock_pci | 0.000|
io_pci_ad<25>| 9.298(R)|clock_pci | 0.000|
io_pci_ad<26>| 9.301(R)|clock_pci | 0.000|
io_pci_ad<27>| 9.395(R)|clock_pci | 0.000|
io_pci_ad<28>| 9.578(R)|clock_pci | 0.000|
io_pci_ad<29>| 9.399(R)|clock_pci | 0.000|
io_pci_ad<30>| 9.177(R)|clock_pci | 0.000|
io_pci_ad<31>| 9.460(R)|clock_pci | 0.000|
io_pci_cbe<0>| 9.262(R)|clock_pci | 0.000|
io_pci_cbe<1>| 9.277(R)|clock_pci | 0.000|
io_pci_cbe<2>| 8.344(R)|clock_pci | 0.000|
io_pci_cbe<3>| 8.942(R)|clock_pci | 0.000|
io_pci_devsel| 8.595(R)|clock_pci | 0.000|
io_pci_frame | 9.124(R)|clock_pci | 0.000|
io_pci_irdy | 8.345(R)|clock_pci | 0.000|
io_pci_stop | 8.320(R)|clock_pci | 0.000|
io_pci_trdy | 9.101(R)|clock_pci | 0.000|
out_pci_par | 7.342(R)|clock_pci | 0.000|
out_pci_req | 9.735(R)|clock_pci | 0.000|
-------------+------------+------------------+--------+
Clock to Setup on destination clock in_pci_clock
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_pci_clock | 17.793| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock in_video_clock
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
in_video_clock | 9.875| 3.731| | |
---------------+---------+---------+---------+---------+
TIMEGRP "pci_in_7" OFFSET = IN 5.62 ns VALID 5.62 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 5.505; Ideal Clock Offset To Actual Clock 0.060;
-------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
-------------+------------+------------+---------+---------+-------------+
in_pci_idsel | 3.942(R)| -0.493(R)| 1.678| 0.493| 0.593|
io_pci_ad<0> | 3.938(R)| -0.489(R)| 1.682| 0.489| 0.597|
io_pci_ad<1> | 3.949(R)| -0.502(R)| 1.671| 0.502| 0.585|
io_pci_ad<2> | 3.938(R)| -0.489(R)| 1.682| 0.489| 0.597|
io_pci_ad<3> | 3.949(R)| -0.502(R)| 1.671| 0.502| 0.585|
io_pci_ad<4> | 3.942(R)| -0.493(R)| 1.678| 0.493| 0.593|
io_pci_ad<5> | 3.963(R)| -0.518(R)| 1.657| 0.518| 0.570|
io_pci_ad<6> | 3.942(R)| -0.493(R)| 1.678| 0.493| 0.593|
io_pci_ad<7> | 3.964(R)| -0.519(R)| 1.656| 0.519| 0.569|
io_pci_ad<8> | 3.964(R)| -0.519(R)| 1.656| 0.519| 0.569|
io_pci_ad<9> | 3.948(R)| -0.500(R)| 1.672| 0.500| 0.586|
io_pci_ad<10>| 3.953(R)| -0.506(R)| 1.667| 0.506| 0.581|
io_pci_ad<11>| 3.967(R)| -0.522(R)| 1.653| 0.522| 0.566|
io_pci_ad<12>| 3.954(R)| -0.507(R)| 1.666| 0.507| 0.579|
io_pci_ad<13>| 3.958(R)| -0.512(R)| 1.662| 0.512| 0.575|
io_pci_ad<14>| 3.965(R)| -0.521(R)| 1.655| 0.521| 0.567|
io_pci_ad<15>| 3.963(R)| -0.518(R)| 1.657| 0.518| 0.570|
io_pci_ad<16>| 3.948(R)| -0.501(R)| 1.672| 0.501| 0.585|
io_pci_ad<17>| 3.951(R)| -0.504(R)| 1.669| 0.504| 0.583|
io_pci_ad<18>| 3.948(R)| -0.501(R)| 1.672| 0.501| 0.585|
io_pci_ad<19>| 3.940(R)| -0.491(R)| 1.680| 0.491| 0.595|
io_pci_ad<20>| 3.964(R)| -0.519(R)| 1.656| 0.519| 0.569|
io_pci_ad<21>| 3.944(R)| -0.496(R)| 1.676| 0.496| 0.590|
io_pci_ad<22>| 3.964(R)| -0.519(R)| 1.656| 0.519| 0.569|
io_pci_ad<23>| 3.944(R)| -0.496(R)| 1.676| 0.496| 0.590|
io_pci_ad<24>| 3.937(R)| -0.488(R)| 1.683| 0.488| 0.598|
io_pci_ad<25>| 3.937(R)| -0.488(R)| 1.683| 0.488| 0.598|
io_pci_ad<26>| 3.938(R)| -0.489(R)| 1.682| 0.489| 0.597|
io_pci_ad<27>| 3.958(R)| -0.512(R)| 1.662| 0.512| 0.575|
io_pci_ad<28>| 3.963(R)| -0.518(R)| 1.657| 0.518| 0.570|
io_pci_ad<29>| 3.963(R)| -0.518(R)| 1.657| 0.518| 0.570|
io_pci_ad<30>| 3.969(R)| -0.525(R)| 1.651| 0.525| 0.563|
io_pci_ad<31>| 3.958(R)| -0.512(R)| 1.662| 0.512| 0.575|
io_pci_cbe<0>| 5.098(R)| -0.500(R)| 0.522| 0.500| 0.011|
io_pci_cbe<1>| 4.652(R)| -0.521(R)| 0.968| 0.521| 0.223|
io_pci_cbe<2>| 4.368(R)| -0.515(R)| 1.252| 0.515| 0.369|
io_pci_cbe<3>| 5.364(R)| -0.491(R)| 0.256| 0.491| -0.118|
io_pci_devsel| 5.047(R)| -0.117(R)| 0.573| 0.117| 0.228|
io_pci_frame | 5.020(R)| -0.360(R)| 0.600| 0.360| 0.120|
io_pci_irdy | 4.758(R)| -0.209(R)| 0.862| 0.209| 0.327|
io_pci_stop | 5.265(R)| -0.197(R)| 0.355| 0.197| 0.079|
io_pci_trdy | 5.622(R)| -0.415(R)| -0.002| 0.415| -0.209|
-------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 5.622| -0.117| -0.002| 0.117| |
-------------+------------+------------+---------+---------+-------------+
TIMEGRP "pci_in_10" OFFSET = IN 8.62 ns VALID 8.62 ns BEFORE COMP "in_pci_clock";
Worst Case Data Window 6.235; Ideal Clock Offset To Actual Clock 0.035;
------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
------------+------------+------------+---------+---------+-------------+
in_pci_gnt | 7.463(R)| -1.228(R)| 1.157| 1.228| -0.035|
------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | 7.463| -1.228| 1.157| 1.228| |
------------+------------+------------+---------+---------+-------------+
TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_rising;
Worst Case Data Window 1.930; Ideal Clock Offset To Actual Clock -0.477;
-------------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
-------------------+------------+------------+---------+---------+-------------+
in_video_data<0> | -0.286(R)| 2.177(R)| 1.656| 0.693| 0.482|
in_video_data<1> | -0.262(R)| 2.148(R)| 1.632| 0.722| 0.455|
in_video_data<2> | -0.299(R)| 2.192(R)| 1.669| 0.678| 0.496|
in_video_data<3> | -0.299(R)| 2.192(R)| 1.669| 0.678| 0.496|
in_video_data<4> | -0.282(R)| 2.172(R)| 1.652| 0.698| 0.477|
in_video_data<5> | -0.282(R)| 2.172(R)| 1.652| 0.698| 0.477|
in_video_data<6> | -0.276(R)| 2.165(R)| 1.646| 0.705| 0.471|
in_video_data<7> | -0.281(R)| 2.171(R)| 1.651| 0.699| 0.476|
in_video_data<8> | -0.285(R)| 2.176(R)| 1.655| 0.694| 0.481|
in_video_data<9> | -0.285(R)| 2.176(R)| 1.655| 0.694| 0.481|
in_video_horizontal| -0.281(R)| 2.171(R)| 1.651| 0.699| 0.476|
-------------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | -0.262| 2.192| 1.632| 0.678| |
-------------------+------------+------------+---------+---------+-------------+
TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_falling;
Worst Case Data Window 1.930; Ideal Clock Offset To Actual Clock -0.477;
----------------+------------+------------+---------+---------+-------------+
| | | Setup | Hold |Source Offset|
Source | Setup | Hold | Slack | Slack | To Center |
----------------+------------+------------+---------+---------+-------------+
in_video_data<0>| -7.026(F)| 8.917(F)| 1.656| 0.693| 0.482|
in_video_data<1>| -7.002(F)| 8.888(F)| 1.632| 0.722| 0.455|
in_video_data<2>| -7.039(F)| 8.932(F)| 1.669| 0.678| 0.496|
in_video_data<3>| -7.039(F)| 8.932(F)| 1.669| 0.678| 0.496|
in_video_data<4>| -7.022(F)| 8.912(F)| 1.652| 0.698| 0.477|
in_video_data<5>| -7.022(F)| 8.912(F)| 1.652| 0.698| 0.477|
in_video_data<6>| -7.016(F)| 8.905(F)| 1.646| 0.705| 0.471|
in_video_data<7>| -7.021(F)| 8.911(F)| 1.651| 0.699| 0.476|
in_video_data<8>| -7.025(F)| 8.916(F)| 1.655| 0.694| 0.481|
in_video_data<9>| -7.025(F)| 8.916(F)| 1.655| 0.694| 0.481|
----------------+------------+------------+---------+---------+-------------+
Worst Case | | | | | |
Summary | -7.002| 8.932| 1.632| 0.678| |
----------------+------------+------------+---------+---------+-------------+
TIMEGRP "pci_out_11" OFFSET = OUT 9.62 ns AFTER COMP "in_pci_clock";
Largest slack: 2.278 ns; Smallest slack: 0.042 ns; Relative Skew: 2.236 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
io_pci_ad<0> | 0.641| 1.637|
io_pci_ad<1> | 0.705| 1.573|
io_pci_ad<2> | 0.463| 1.815|
io_pci_ad<3> | 0.828| 1.450|
io_pci_ad<4> | 0.390| 1.888|
io_pci_ad<5> | 0.554| 1.724|
io_pci_ad<6> | 0.452| 1.826|
io_pci_ad<7> | 0.198| 2.080|
io_pci_ad<8> | 0.531| 1.747|
io_pci_ad<9> | 0.174| 2.104|
io_pci_ad<10> | 0.805| 1.473|
io_pci_ad<11> | 0.303| 1.975|
io_pci_ad<12> | 1.042| 1.236|
io_pci_ad<13> | 0.561| 1.717|
io_pci_ad<14> | 1.144| 1.134|
io_pci_ad<15> | 0.275| 2.003|
io_pci_ad<16> | 0.917| 1.361|
io_pci_ad<17> | 0.709| 1.569|
io_pci_ad<18> | 0.645| 1.633|
io_pci_ad<19> | 0.767| 1.511|
io_pci_ad<20> | 0.391| 1.887|
io_pci_ad<21> | 0.778| 1.500|
io_pci_ad<22> | 0.521| 1.757|
io_pci_ad<23> | 0.598| 1.680|
io_pci_ad<24> | 0.351| 1.927|
io_pci_ad<25> | 0.322| 1.956|
io_pci_ad<26> | 0.319| 1.959|
io_pci_ad<27> | 0.225| 2.053|
io_pci_ad<28> | 0.042| 2.236|
io_pci_ad<29> | 0.221| 2.057|
io_pci_ad<30> | 0.443| 1.835|
io_pci_ad<31> | 0.160| 2.118|
io_pci_cbe<0> | 0.358| 1.920|
io_pci_cbe<1> | 0.343| 1.935|
io_pci_cbe<2> | 1.276| 1.002|
io_pci_cbe<3> | 0.678| 1.600|
io_pci_devsel | 1.025| 1.253|
io_pci_frame | 0.496| 1.782|
io_pci_irdy | 1.275| 1.003|
io_pci_stop | 1.300| 0.978|
io_pci_trdy | 0.519| 1.759|
out_pci_par | 2.278| 0.000|
-----------------------------------------------+-------------+-------------+
TIMEGRP "pci_out_12" OFFSET = OUT 10.62 ns AFTER COMP "in_pci_clock";
Largest slack: 0.885 ns; Smallest slack: 0.885 ns; Relative Skew: 0.000 ns;
-----------------------------------------------+-------------+-------------+
PAD | Slack |Relative Skew|
-----------------------------------------------+-------------+-------------+
out_pci_req | 0.885| 0.000|
-----------------------------------------------+-------------+-------------+
Timing summary:
---------------
Timing errors: 1 Score: 2
Constraints cover 116770 paths, 0 nets, and 10497 connections
Design statistics:
Minimum period: 17.793ns (Maximum frequency: 56.202MHz)
Minimum input required time before clock: 7.463ns
Minimum output required time after clock: 9.735ns
Analysis completed SAT 15 MAR 20:43:15 2008
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 134 MB