PCI のセットアップと出力遅延は、バススイッチの伝播遅延を考慮して、規格より 1.2ns 厳しい制約条件にしました。
-------------------------------------------------------------------------------- Release 9.1.03i Trace Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. K:\ISE\bin\nt\trce.exe -ise E:/RTL/_/PV.ise -intstyle ise -e 3 -s 4 -xml PV PV.ncd -o PV.twr PV.pcf -ucf E:/RTL/Code/UCF/PV.ucf Design file: pv.ncd Physical constraint file: pv.pcf Device,package,speed: xc3s500e,ft256,-4 (PRODUCTION 1.26 2006-10-19) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: TS_pci_clock = PERIOD TIMEGRP "pci_clock" 30 ns HIGH 50%; 32363 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 23.193ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_video_clock = PERIOD TIMEGRP "video_clock" 13.48 ns HIGH 50%; 39138 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 10.202ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clock_pci_rx_clock = PERIOD TIMEGRP "clock_pci_rx_clock" TS_pci_clock * 2 HIGH 50%; 13062 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 11.688ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clock_pci_ram_clock = PERIOD TIMEGRP "clock_pci_ram_clock" TS_pci_clock / 3 HIGH 50%; 5688 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 8.989ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "pci_in_7" OFFSET = IN 5.8 ns VALID 5.8 ns BEFORE COMP "in_pci_clock"; 282 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 5.738ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "pci_in_10" OFFSET = IN 8.8 ns VALID 8.8 ns BEFORE COMP "in_pci_clock"; 10 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 4.502ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "pci_out_11" OFFSET = OUT 9.8 ns AFTER COMP "in_pci_clock"; 84 items analyzed, 0 timing errors detected. Minimum allowable offset is 9.595ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "pci_out_12" OFFSET = OUT 10.8 ns AFTER COMP "in_pci_clock"; 2 items analyzed, 0 timing errors detected. Minimum allowable offset is 7.383ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_rising; 11 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Offset is -0.263ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_falling; 10 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Offset is -7.003ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "ram_in" OFFSET = IN 8 ns VALID 16 ns BEFORE COMP "in_pci_clock"; 38 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 0.743ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "ram_out" OFFSET = OUT 15 ns AFTER COMP "in_pci_clock"; 161 items analyzed, 0 timing errors detected. Minimum allowable offset is 14.225ns. -------------------------------------------------------------------------------- All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock in_pci_clock ---------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ---------------+------------+------------+------------------+--------+ in_pci_gnt | 4.502(R)| -0.089(R)|clock_pci | 0.000| in_pci_idsel | 3.943(R)| -0.493(R)|clock_pci | 0.000| io_pci_ad<0> | 3.939(R)| -0.489(R)|clock_pci | 0.000| io_pci_ad<1> | 3.950(R)| -0.502(R)|clock_pci | 0.000| io_pci_ad<2> | 3.939(R)| -0.489(R)|clock_pci | 0.000| io_pci_ad<3> | 3.950(R)| -0.502(R)|clock_pci | 0.000| io_pci_ad<4> | 3.943(R)| -0.493(R)|clock_pci | 0.000| io_pci_ad<5> | 3.964(R)| -0.518(R)|clock_pci | 0.000| io_pci_ad<6> | 3.943(R)| -0.493(R)|clock_pci | 0.000| io_pci_ad<7> | 3.965(R)| -0.519(R)|clock_pci | 0.000| io_pci_ad<8> | 3.965(R)| -0.519(R)|clock_pci | 0.000| io_pci_ad<9> | 3.949(R)| -0.500(R)|clock_pci | 0.000| io_pci_ad<10> | 3.954(R)| -0.506(R)|clock_pci | 0.000| io_pci_ad<11> | 3.968(R)| -0.522(R)|clock_pci | 0.000| io_pci_ad<12> | 3.955(R)| -0.507(R)|clock_pci | 0.000| io_pci_ad<13> | 3.959(R)| -0.512(R)|clock_pci | 0.000| io_pci_ad<14> | 3.966(R)| -0.521(R)|clock_pci | 0.000| io_pci_ad<15> | 3.964(R)| -0.518(R)|clock_pci | 0.000| io_pci_ad<16> | 3.949(R)| -0.501(R)|clock_pci | 0.000| io_pci_ad<17> | 3.952(R)| -0.504(R)|clock_pci | 0.000| io_pci_ad<18> | 3.949(R)| -0.501(R)|clock_pci | 0.000| io_pci_ad<19> | 3.941(R)| -0.491(R)|clock_pci | 0.000| io_pci_ad<20> | 3.965(R)| -0.519(R)|clock_pci | 0.000| io_pci_ad<21> | 3.945(R)| -0.496(R)|clock_pci | 0.000| io_pci_ad<22> | 3.965(R)| -0.519(R)|clock_pci | 0.000| io_pci_ad<23> | 3.945(R)| -0.496(R)|clock_pci | 0.000| io_pci_ad<24> | 3.938(R)| -0.488(R)|clock_pci | 0.000| io_pci_ad<25> | 3.938(R)| -0.488(R)|clock_pci | 0.000| io_pci_ad<26> | 3.940(R)| -0.489(R)|clock_pci | 0.000| io_pci_ad<27> | 3.959(R)| -0.512(R)|clock_pci | 0.000| io_pci_ad<28> | 3.964(R)| -0.518(R)|clock_pci | 0.000| io_pci_ad<29> | 3.964(R)| -0.518(R)|clock_pci | 0.000| io_pci_ad<30> | 3.971(R)| -0.526(R)|clock_pci | 0.000| io_pci_ad<31> | 3.959(R)| -0.512(R)|clock_pci | 0.000| io_pci_cbe<0> | 3.949(R)| -0.500(R)|clock_pci | 0.000| io_pci_cbe<1> | 3.966(R)| -0.521(R)|clock_pci | 0.000| io_pci_cbe<2> | 3.961(R)| -0.515(R)|clock_pci | 0.000| io_pci_cbe<3> | 3.941(R)| -0.491(R)|clock_pci | 0.000| io_pci_devsel | 4.323(R)| -0.341(R)|clock_pci | 0.000| io_pci_frame | 3.716(R)| -0.291(R)|clock_pci | 0.000| io_pci_irdy | 3.752(R)| -0.198(R)|clock_pci | 0.000| io_pci_stop | 3.717(R)| -0.408(R)|clock_pci | 0.000| io_pci_trdy | 5.738(R)| -0.285(R)|clock_pci | 0.000| io_ram_data<0> | 0.726(R)| 2.047(R)|clock_ram | 0.000| io_ram_data<1> | 0.743(R)| 2.027(R)|clock_ram | 0.000| io_ram_data<2> | 0.717(R)| 2.058(R)|clock_ram | 0.000| io_ram_data<3> | 0.731(R)| 2.041(R)|clock_ram | 0.000| io_ram_data<4> | 0.717(R)| 2.058(R)|clock_ram | 0.000| io_ram_data<5> | 0.731(R)| 2.041(R)|clock_ram | 0.000| io_ram_data<6> | 0.722(R)| 2.052(R)|clock_ram | 0.000| io_ram_data<7> | 0.732(R)| 2.040(R)|clock_ram | 0.000| io_ram_data<8> | 0.741(R)| 2.030(R)|clock_ram | 0.000| io_ram_data<9> | 0.716(R)| 2.059(R)|clock_ram | 0.000| io_ram_data<10>| 0.736(R)| 2.036(R)|clock_ram | 0.000| io_ram_data<11>| 0.715(R)| 2.061(R)|clock_ram | 0.000| io_ram_data<12>| 0.716(R)| 2.059(R)|clock_ram | 0.000| io_ram_data<13>| 0.715(R)| 2.061(R)|clock_ram | 0.000| io_ram_data<14>| 0.722(R)| 2.052(R)|clock_ram | 0.000| io_ram_data<15>| 0.742(R)| 2.029(R)|clock_ram | 0.000| io_ram_data<16>| 0.731(R)| 2.042(R)|clock_ram | 0.000| io_ram_data<17>| 0.727(R)| 2.046(R)|clock_ram | 0.000| io_ram_data<18>| 0.726(R)| 2.048(R)|clock_ram | 0.000| io_ram_data<19>| 0.742(R)| 2.029(R)|clock_ram | 0.000| io_ram_data<20>| 0.741(R)| 2.030(R)|clock_ram | 0.000| io_ram_data<21>| 0.726(R)| 2.048(R)|clock_ram | 0.000| io_ram_data<22>| 0.732(R)| 2.040(R)|clock_ram | 0.000| io_ram_data<23>| 0.743(R)| 2.027(R)|clock_ram | 0.000| io_ram_data<24>| -0.267(R)| 2.157(R)|clock_pci | 0.000| | 0.739(R)| 2.032(R)|clock_ram | 0.000| io_ram_data<25>| -0.271(R)| 2.161(R)|clock_pci | 0.000| | 0.736(R)| 2.036(R)|clock_ram | 0.000| io_ram_data<26>| 0.743(R)| 2.028(R)|clock_ram | 0.000| io_ram_data<27>| -0.275(R)| 2.165(R)|clock_pci | 0.000| | 0.732(R)| 2.041(R)|clock_ram | 0.000| io_ram_data<28>| 0.743(R)| 2.028(R)|clock_ram | 0.000| io_ram_data<29>| -0.275(R)| 2.165(R)|clock_pci | 0.000| | 0.732(R)| 2.041(R)|clock_ram | 0.000| io_ram_data<30>| -0.273(R)| 2.164(R)|clock_pci | 0.000| | 0.733(R)| 2.039(R)|clock_ram | 0.000| io_ram_data<31>| -0.273(R)| 2.164(R)|clock_pci | 0.000| | 0.733(R)| 2.039(R)|clock_ram | 0.000| ---------------+------------+------------+------------------+--------+ Setup/Hold to clock in_video_clock -------------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | -------------------+------------+------------+------------------+--------+ in_video_data<0> | -0.287(R)| 2.177(R)|clock_video | 0.000| | -7.027(F)| 8.917(F)|clock_video | 6.740| in_video_data<1> | -0.263(R)| 2.148(R)|clock_video | 0.000| | -7.003(F)| 8.888(F)|clock_video | 6.740| in_video_data<2> | -0.299(R)| 2.192(R)|clock_video | 0.000| | -7.039(F)| 8.932(F)|clock_video | 6.740| in_video_data<3> | -0.299(R)| 2.192(R)|clock_video | 0.000| | -7.039(F)| 8.932(F)|clock_video | 6.740| in_video_data<4> | -0.283(R)| 2.172(R)|clock_video | 0.000| | -7.023(F)| 8.912(F)|clock_video | 6.740| in_video_data<5> | -0.283(R)| 2.172(R)|clock_video | 0.000| | -7.023(F)| 8.912(F)|clock_video | 6.740| in_video_data<6> | -0.277(R)| 2.165(R)|clock_video | 0.000| | -7.017(F)| 8.905(F)|clock_video | 6.740| in_video_data<7> | -0.281(R)| 2.169(R)|clock_video | 0.000| | -7.021(F)| 8.909(F)|clock_video | 6.740| in_video_data<8> | -0.286(R)| 2.176(R)|clock_video | 0.000| | -7.026(F)| 8.916(F)|clock_video | 6.740| in_video_data<9> | -0.286(R)| 2.176(R)|clock_video | 0.000| | -7.026(F)| 8.916(F)|clock_video | 6.740| in_video_horizontal| -0.282(R)| 2.171(R)|clock_video | 0.000| -------------------+------------+------------+------------------+--------+ Clock in_pci_clock to Pad --------------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | --------------------+------------+------------------+--------+ io_pci_ad<0> | 9.471(R)|clock_pci | 0.000| io_pci_ad<1> | 9.253(R)|clock_pci | 0.000| io_pci_ad<2> | 9.216(R)|clock_pci | 0.000| io_pci_ad<3> | 8.949(R)|clock_pci | 0.000| io_pci_ad<4> | 9.214(R)|clock_pci | 0.000| io_pci_ad<5> | 9.117(R)|clock_pci | 0.000| io_pci_ad<6> | 9.201(R)|clock_pci | 0.000| io_pci_ad<7> | 8.918(R)|clock_pci | 0.000| io_pci_ad<8> | 9.203(R)|clock_pci | 0.000| io_pci_ad<9> | 9.255(R)|clock_pci | 0.000| io_pci_ad<10> | 8.507(R)|clock_pci | 0.000| io_pci_ad<11> | 9.198(R)|clock_pci | 0.000| io_pci_ad<12> | 8.459(R)|clock_pci | 0.000| io_pci_ad<13> | 8.820(R)|clock_pci | 0.000| io_pci_ad<14> | 8.591(R)|clock_pci | 0.000| io_pci_ad<15> | 9.135(R)|clock_pci | 0.000| io_pci_ad<16> | 8.525(R)|clock_pci | 0.000| io_pci_ad<17> | 8.863(R)|clock_pci | 0.000| io_pci_ad<18> | 8.536(R)|clock_pci | 0.000| io_pci_ad<19> | 8.905(R)|clock_pci | 0.000| io_pci_ad<20> | 8.410(R)|clock_pci | 0.000| io_pci_ad<21> | 8.985(R)|clock_pci | 0.000| io_pci_ad<22> | 8.924(R)|clock_pci | 0.000| io_pci_ad<23> | 8.958(R)|clock_pci | 0.000| io_pci_ad<24> | 8.966(R)|clock_pci | 0.000| io_pci_ad<25> | 9.008(R)|clock_pci | 0.000| io_pci_ad<26> | 9.247(R)|clock_pci | 0.000| io_pci_ad<27> | 8.970(R)|clock_pci | 0.000| io_pci_ad<28> | 9.148(R)|clock_pci | 0.000| io_pci_ad<29> | 9.151(R)|clock_pci | 0.000| io_pci_ad<30> | 9.212(R)|clock_pci | 0.000| io_pci_ad<31> | 9.595(R)|clock_pci | 0.000| io_pci_cbe<0> | 9.459(R)|clock_pci | 0.000| io_pci_cbe<1> | 8.923(R)|clock_pci | 0.000| io_pci_cbe<2> | 9.170(R)|clock_pci | 0.000| io_pci_cbe<3> | 8.936(R)|clock_pci | 0.000| io_pci_devsel | 8.193(R)|clock_pci | 0.000| io_pci_frame | 8.024(R)|clock_pci | 0.000| io_pci_irdy | 8.380(R)|clock_pci | 0.000| io_pci_stop | 8.071(R)|clock_pci | 0.000| io_pci_trdy | 8.208(R)|clock_pci | 0.000| io_ram_data<0> | 10.397(R)|clock_ram | 0.000| io_ram_data<1> | 12.194(R)|clock_pci | 0.000| | 12.439(R)|clock_ram | 0.000| io_ram_data<2> | 13.722(R)|clock_pci | 0.000| | 14.225(R)|clock_ram | 0.000| io_ram_data<3> | 12.130(R)|clock_pci | 0.000| | 12.776(R)|clock_ram | 0.000| io_ram_data<4> | 12.499(R)|clock_pci | 0.000| | 13.145(R)|clock_ram | 0.000| io_ram_data<5> | 12.390(R)|clock_pci | 0.000| | 13.036(R)|clock_ram | 0.000| io_ram_data<6> | 10.619(R)|clock_ram | 0.000| io_ram_data<7> | 12.266(R)|clock_pci | 0.000| | 12.912(R)|clock_ram | 0.000| io_ram_data<8> | 10.429(R)|clock_ram | 0.000| io_ram_data<9> | 10.743(R)|clock_ram | 0.000| io_ram_data<10> | 10.199(R)|clock_ram | 0.000| io_ram_data<11> | 13.032(R)|clock_pci | 0.000| | 13.678(R)|clock_ram | 0.000| io_ram_data<12> | 13.338(R)|clock_pci | 0.000| | 13.984(R)|clock_ram | 0.000| io_ram_data<13> | 13.308(R)|clock_pci | 0.000| | 13.954(R)|clock_ram | 0.000| io_ram_data<14> | 10.369(R)|clock_ram | 0.000| io_ram_data<15> | 10.748(R)|clock_ram | 0.000| io_ram_data<16> | 13.048(R)|clock_pci | 0.000| | 13.694(R)|clock_ram | 0.000| io_ram_data<17> | 12.865(R)|clock_ram | 0.000| io_ram_data<18> | 12.359(R)|clock_ram | 0.000| io_ram_data<19> | 11.500(R)|clock_ram | 0.000| io_ram_data<20> | 12.767(R)|clock_pci | 0.000| | 13.180(R)|clock_ram | 0.000| io_ram_data<21> | 12.370(R)|clock_ram | 0.000| io_ram_data<22> | 12.797(R)|clock_pci | 0.000| | 13.443(R)|clock_ram | 0.000| io_ram_data<23> | 11.771(R)|clock_pci | 0.000| | 12.417(R)|clock_ram | 0.000| io_ram_data<24> | 13.191(R)|clock_pci | 0.000| | 12.255(R)|clock_ram | 0.000| io_ram_data<25> | 13.593(R)|clock_pci | 0.000| | 12.657(R)|clock_ram | 0.000| io_ram_data<26> | 10.907(R)|clock_ram | 0.000| io_ram_data<27> | 12.906(R)|clock_pci | 0.000| | 11.970(R)|clock_ram | 0.000| io_ram_data<28> | 10.442(R)|clock_ram | 0.000| io_ram_data<29> | 12.703(R)|clock_pci | 0.000| | 11.767(R)|clock_ram | 0.000| io_ram_data<30> | 12.914(R)|clock_pci | 0.000| | 11.978(R)|clock_ram | 0.000| io_ram_data<31> | 13.205(R)|clock_pci | 0.000| | 11.676(R)|clock_ram | 0.000| out_pci_par | 7.342(R)|clock_pci | 0.000| out_pci_req | 7.383(R)|clock_pci | 0.000| out_ram_address<0> | 13.778(R)|clock_pci | 0.000| | 13.397(R)|clock_ram | 0.000| out_ram_address<1> | 13.206(R)|clock_pci | 0.000| | 12.349(R)|clock_ram | 0.000| out_ram_address<2> | 7.685(R)|clock_ram | 0.000| out_ram_address<3> | 7.648(R)|clock_ram | 0.000| out_ram_address<4> | 7.648(R)|clock_ram | 0.000| out_ram_address<5> | 7.656(R)|clock_ram | 0.000| out_ram_address<6> | 12.614(R)|clock_pci | 0.000| | 10.334(R)|clock_ram | 0.000| out_ram_address<7> | 13.507(R)|clock_pci | 0.000| | 11.210(R)|clock_ram | 0.000| out_ram_address<8> | 7.633(R)|clock_ram | 0.000| out_ram_address<9> | 7.648(R)|clock_ram | 0.000| out_ram_address<10> | 12.170(R)|clock_pci | 0.000| | 12.111(R)|clock_ram | 0.000| out_ram_bank<0> | 13.046(R)|clock_pci | 0.000| | 12.061(R)|clock_ram | 0.000| out_ram_bank<1> | 13.242(R)|clock_pci | 0.000| | 11.671(R)|clock_ram | 0.000| out_ram_col_address | 7.670(R)|clock_ram | 0.000| out_ram_row_address | 7.655(R)|clock_ram | 0.000| out_ram_write_enable| 7.670(R)|clock_ram | 0.000| --------------------+------------+------------------+--------+ Clock to Setup on destination clock in_pci_clock ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ in_pci_clock | 14.139| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock in_video_clock ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ in_video_clock | 10.202| 3.417| | 3.653| ---------------+---------+---------+---------+---------+ TIMEGRP "pci_in_7" OFFSET = IN 5.8 ns VALID 5.8 ns BEFORE COMP "in_pci_clock"; Worst Case Data Window 5.540; Ideal Clock Offset To Actual Clock 0.068; -------------+------------+------------+---------+---------+-------------+ | | | Setup | Hold |Source Offset| Source | Setup | Hold | Slack | Slack | To Center | -------------+------------+------------+---------+---------+-------------+ in_pci_idsel | 3.943(R)| -0.493(R)| 1.857| 0.493| 0.682| io_pci_ad<0> | 3.939(R)| -0.489(R)| 1.861| 0.489| 0.686| io_pci_ad<1> | 3.950(R)| -0.502(R)| 1.850| 0.502| 0.674| io_pci_ad<2> | 3.939(R)| -0.489(R)| 1.861| 0.489| 0.686| io_pci_ad<3> | 3.950(R)| -0.502(R)| 1.850| 0.502| 0.674| io_pci_ad<4> | 3.943(R)| -0.493(R)| 1.857| 0.493| 0.682| io_pci_ad<5> | 3.964(R)| -0.518(R)| 1.836| 0.518| 0.659| io_pci_ad<6> | 3.943(R)| -0.493(R)| 1.857| 0.493| 0.682| io_pci_ad<7> | 3.965(R)| -0.519(R)| 1.835| 0.519| 0.658| io_pci_ad<8> | 3.965(R)| -0.519(R)| 1.835| 0.519| 0.658| io_pci_ad<9> | 3.949(R)| -0.500(R)| 1.851| 0.500| 0.676| io_pci_ad<10>| 3.954(R)| -0.506(R)| 1.846| 0.506| 0.670| io_pci_ad<11>| 3.968(R)| -0.522(R)| 1.832| 0.522| 0.655| io_pci_ad<12>| 3.955(R)| -0.507(R)| 1.845| 0.507| 0.669| io_pci_ad<13>| 3.959(R)| -0.512(R)| 1.841| 0.512| 0.665| io_pci_ad<14>| 3.966(R)| -0.521(R)| 1.834| 0.521| 0.657| io_pci_ad<15>| 3.964(R)| -0.518(R)| 1.836| 0.518| 0.659| io_pci_ad<16>| 3.949(R)| -0.501(R)| 1.851| 0.501| 0.675| io_pci_ad<17>| 3.952(R)| -0.504(R)| 1.848| 0.504| 0.672| io_pci_ad<18>| 3.949(R)| -0.501(R)| 1.851| 0.501| 0.675| io_pci_ad<19>| 3.941(R)| -0.491(R)| 1.859| 0.491| 0.684| io_pci_ad<20>| 3.965(R)| -0.519(R)| 1.835| 0.519| 0.658| io_pci_ad<21>| 3.945(R)| -0.496(R)| 1.855| 0.496| 0.680| io_pci_ad<22>| 3.965(R)| -0.519(R)| 1.835| 0.519| 0.658| io_pci_ad<23>| 3.945(R)| -0.496(R)| 1.855| 0.496| 0.680| io_pci_ad<24>| 3.938(R)| -0.488(R)| 1.862| 0.488| 0.687| io_pci_ad<25>| 3.938(R)| -0.488(R)| 1.862| 0.488| 0.687| io_pci_ad<26>| 3.940(R)| -0.489(R)| 1.860| 0.489| 0.686| io_pci_ad<27>| 3.959(R)| -0.512(R)| 1.841| 0.512| 0.665| io_pci_ad<28>| 3.964(R)| -0.518(R)| 1.836| 0.518| 0.659| io_pci_ad<29>| 3.964(R)| -0.518(R)| 1.836| 0.518| 0.659| io_pci_ad<30>| 3.971(R)| -0.526(R)| 1.829| 0.526| 0.652| io_pci_ad<31>| 3.959(R)| -0.512(R)| 1.841| 0.512| 0.665| io_pci_cbe<0>| 3.949(R)| -0.500(R)| 1.851| 0.500| 0.676| io_pci_cbe<1>| 3.966(R)| -0.521(R)| 1.834| 0.521| 0.657| io_pci_cbe<2>| 3.961(R)| -0.515(R)| 1.839| 0.515| 0.662| io_pci_cbe<3>| 3.941(R)| -0.491(R)| 1.859| 0.491| 0.684| io_pci_devsel| 4.323(R)| -0.341(R)| 1.477| 0.341| 0.568| io_pci_frame | 3.716(R)| -0.291(R)| 2.084| 0.291| 0.897| io_pci_irdy | 3.752(R)| -0.198(R)| 2.048| 0.198| 0.925| io_pci_stop | 3.717(R)| -0.408(R)| 2.083| 0.408| 0.838| io_pci_trdy | 5.738(R)| -0.285(R)| 0.062| 0.285| -0.111| -------------+------------+------------+---------+---------+-------------+ Worst Case | | | | | | Summary | 5.738| -0.198| 0.062| 0.198| | -------------+------------+------------+---------+---------+-------------+ TIMEGRP "pci_in_10" OFFSET = IN 8.8 ns VALID 8.8 ns BEFORE COMP "in_pci_clock"; Worst Case Data Window 4.413; Ideal Clock Offset To Actual Clock -2.104; ------------+------------+------------+---------+---------+-------------+ | | | Setup | Hold |Source Offset| Source | Setup | Hold | Slack | Slack | To Center | ------------+------------+------------+---------+---------+-------------+ in_pci_gnt | 4.502(R)| -0.089(R)| 4.298| 0.089| 2.104| ------------+------------+------------+---------+---------+-------------+ Worst Case | | | | | | Summary | 4.502| -0.089| 4.298| 0.089| | ------------+------------+------------+---------+---------+-------------+ TIMEGRP "video_in" OFFSET = IN 1.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_rising; Worst Case Data Window 1.929; Ideal Clock Offset To Actual Clock -0.478; -------------------+------------+------------+---------+---------+-------------+ | | | Setup | Hold |Source Offset| Source | Setup | Hold | Slack | Slack | To Center | -------------------+------------+------------+---------+---------+-------------+ in_video_data<0> | -0.287(R)| 2.177(R)| 1.657| 0.693| 0.482| in_video_data<1> | -0.263(R)| 2.148(R)| 1.633| 0.722| 0.456| in_video_data<2> | -0.299(R)| 2.192(R)| 1.669| 0.678| 0.496| in_video_data<3> | -0.299(R)| 2.192(R)| 1.669| 0.678| 0.496| in_video_data<4> | -0.283(R)| 2.172(R)| 1.653| 0.698| 0.478| in_video_data<5> | -0.283(R)| 2.172(R)| 1.653| 0.698| 0.478| in_video_data<6> | -0.277(R)| 2.165(R)| 1.647| 0.705| 0.471| in_video_data<7> | -0.281(R)| 2.169(R)| 1.651| 0.701| 0.475| in_video_data<8> | -0.286(R)| 2.176(R)| 1.656| 0.694| 0.481| in_video_data<9> | -0.286(R)| 2.176(R)| 1.656| 0.694| 0.481| in_video_horizontal| -0.282(R)| 2.171(R)| 1.652| 0.699| 0.477| -------------------+------------+------------+---------+---------+-------------+ Worst Case | | | | | | Summary | -0.263| 2.192| 1.633| 0.678| | -------------------+------------+------------+---------+---------+-------------+ TIMEGRP "video_in" OFFSET = IN -5.37 ns VALID 4.24 ns BEFORE COMP "in_video_clock" TIMEGRP video_falling; Worst Case Data Window 1.929; Ideal Clock Offset To Actual Clock -0.478; ----------------+------------+------------+---------+---------+-------------+ | | | Setup | Hold |Source Offset| Source | Setup | Hold | Slack | Slack | To Center | ----------------+------------+------------+---------+---------+-------------+ in_video_data<0>| -7.027(F)| 8.917(F)| 1.657| 0.693| 0.482| in_video_data<1>| -7.003(F)| 8.888(F)| 1.633| 0.722| 0.456| in_video_data<2>| -7.039(F)| 8.932(F)| 1.669| 0.678| 0.496| in_video_data<3>| -7.039(F)| 8.932(F)| 1.669| 0.678| 0.496| in_video_data<4>| -7.023(F)| 8.912(F)| 1.653| 0.698| 0.478| in_video_data<5>| -7.023(F)| 8.912(F)| 1.653| 0.698| 0.478| in_video_data<6>| -7.017(F)| 8.905(F)| 1.647| 0.705| 0.471| in_video_data<7>| -7.021(F)| 8.909(F)| 1.651| 0.701| 0.475| in_video_data<8>| -7.026(F)| 8.916(F)| 1.656| 0.694| 0.481| in_video_data<9>| -7.026(F)| 8.916(F)| 1.656| 0.694| 0.481| ----------------+------------+------------+---------+---------+-------------+ Worst Case | | | | | | Summary | -7.003| 8.932| 1.633| 0.678| | ----------------+------------+------------+---------+---------+-------------+ TIMEGRP "ram_in" OFFSET = IN 8 ns VALID 16 ns BEFORE COMP "in_pci_clock"; Worst Case Data Window 2.908; Ideal Clock Offset To Actual Clock -0.711; ---------------+------------+------------+---------+---------+-------------+ | | | Setup | Hold |Source Offset| Source | Setup | Hold | Slack | Slack | To Center | ---------------+------------+------------+---------+---------+-------------+ io_ram_data<0> | 0.726(R)| 2.047(R)| 7.274| 5.953| 0.660| io_ram_data<1> | 0.743(R)| 2.027(R)| 7.257| 5.973| 0.642| io_ram_data<2> | 0.717(R)| 2.058(R)| 7.283| 5.942| 0.671| io_ram_data<3> | 0.731(R)| 2.041(R)| 7.269| 5.959| 0.655| io_ram_data<4> | 0.717(R)| 2.058(R)| 7.283| 5.942| 0.671| io_ram_data<5> | 0.731(R)| 2.041(R)| 7.269| 5.959| 0.655| io_ram_data<6> | 0.722(R)| 2.052(R)| 7.278| 5.948| 0.665| io_ram_data<7> | 0.732(R)| 2.040(R)| 7.268| 5.960| 0.654| io_ram_data<8> | 0.741(R)| 2.030(R)| 7.259| 5.970| 0.645| io_ram_data<9> | 0.716(R)| 2.059(R)| 7.284| 5.941| 0.672| io_ram_data<10>| 0.736(R)| 2.036(R)| 7.264| 5.964| 0.650| io_ram_data<11>| 0.715(R)| 2.061(R)| 7.285| 5.939| 0.673| io_ram_data<12>| 0.716(R)| 2.059(R)| 7.284| 5.941| 0.672| io_ram_data<13>| 0.715(R)| 2.061(R)| 7.285| 5.939| 0.673| io_ram_data<14>| 0.722(R)| 2.052(R)| 7.278| 5.948| 0.665| io_ram_data<15>| 0.742(R)| 2.029(R)| 7.258| 5.971| 0.644| io_ram_data<16>| 0.731(R)| 2.042(R)| 7.269| 5.958| 0.656| io_ram_data<17>| 0.727(R)| 2.046(R)| 7.273| 5.954| 0.660| io_ram_data<18>| 0.726(R)| 2.048(R)| 7.274| 5.952| 0.661| io_ram_data<19>| 0.742(R)| 2.029(R)| 7.258| 5.971| 0.644| io_ram_data<20>| 0.741(R)| 2.030(R)| 7.259| 5.970| 0.645| io_ram_data<21>| 0.726(R)| 2.048(R)| 7.274| 5.952| 0.661| io_ram_data<22>| 0.732(R)| 2.040(R)| 7.268| 5.960| 0.654| io_ram_data<23>| 0.743(R)| 2.027(R)| 7.257| 5.973| 0.642| io_ram_data<24>| -0.267(R)| 2.157(R)| 8.267| 5.843| 1.212| | 0.739(R)| 2.032(R)| 7.261| 5.968| 0.647| io_ram_data<25>| -0.271(R)| 2.161(R)| 8.271| 5.839| 1.216| | 0.736(R)| 2.036(R)| 7.264| 5.964| 0.650| io_ram_data<26>| 0.743(R)| 2.028(R)| 7.257| 5.972| 0.642| io_ram_data<27>| -0.275(R)| 2.165(R)| 8.275| 5.835| 1.220| | 0.732(R)| 2.041(R)| 7.268| 5.959| 0.655| io_ram_data<28>| 0.743(R)| 2.028(R)| 7.257| 5.972| 0.642| io_ram_data<29>| -0.275(R)| 2.165(R)| 8.275| 5.835| 1.220| | 0.732(R)| 2.041(R)| 7.268| 5.959| 0.655| io_ram_data<30>| -0.273(R)| 2.164(R)| 8.273| 5.836| 1.218| | 0.733(R)| 2.039(R)| 7.267| 5.961| 0.653| io_ram_data<31>| -0.273(R)| 2.164(R)| 8.273| 5.836| 1.218| | 0.733(R)| 2.039(R)| 7.267| 5.961| 0.653| ---------------+------------+------------+---------+---------+-------------+ Worst Case | | | | | | Summary | 0.743| 2.165| 7.257| 5.835| | ---------------+------------+------------+---------+---------+-------------+ TIMEGRP "pci_out_11" OFFSET = OUT 9.8 ns AFTER COMP "in_pci_clock"; Largest slack: 2.458 ns; Smallest slack: 0.205 ns; Relative Skew: 2.253 ns; -----------------------------------------------+-------------+-------------+ PAD | Slack |Relative Skew| -----------------------------------------------+-------------+-------------+ io_pci_ad<0> | 0.329| 2.129| io_pci_ad<1> | 0.547| 1.911| io_pci_ad<2> | 0.584| 1.874| io_pci_ad<3> | 0.851| 1.607| io_pci_ad<4> | 0.586| 1.872| io_pci_ad<5> | 0.683| 1.775| io_pci_ad<6> | 0.599| 1.859| io_pci_ad<7> | 0.882| 1.576| io_pci_ad<8> | 0.597| 1.861| io_pci_ad<9> | 0.545| 1.913| io_pci_ad<10> | 1.293| 1.165| io_pci_ad<11> | 0.602| 1.856| io_pci_ad<12> | 1.341| 1.117| io_pci_ad<13> | 0.980| 1.478| io_pci_ad<14> | 1.209| 1.249| io_pci_ad<15> | 0.665| 1.793| io_pci_ad<16> | 1.275| 1.183| io_pci_ad<17> | 0.937| 1.521| io_pci_ad<18> | 1.264| 1.194| io_pci_ad<19> | 0.895| 1.563| io_pci_ad<20> | 1.390| 1.068| io_pci_ad<21> | 0.815| 1.643| io_pci_ad<22> | 0.876| 1.582| io_pci_ad<23> | 0.842| 1.616| io_pci_ad<24> | 0.834| 1.624| io_pci_ad<25> | 0.792| 1.666| io_pci_ad<26> | 0.553| 1.905| io_pci_ad<27> | 0.830| 1.628| io_pci_ad<28> | 0.652| 1.806| io_pci_ad<29> | 0.649| 1.809| io_pci_ad<30> | 0.588| 1.870| io_pci_ad<31> | 0.205| 2.253| io_pci_cbe<0> | 0.341| 2.117| io_pci_cbe<1> | 0.877| 1.581| io_pci_cbe<2> | 0.630| 1.828| io_pci_cbe<3> | 0.864| 1.594| io_pci_devsel | 1.607| 0.851| io_pci_frame | 1.776| 0.682| io_pci_irdy | 1.420| 1.038| io_pci_stop | 1.729| 0.729| io_pci_trdy | 1.592| 0.866| out_pci_par | 2.458| 0.000| -----------------------------------------------+-------------+-------------+ TIMEGRP "pci_out_12" OFFSET = OUT 10.8 ns AFTER COMP "in_pci_clock"; Largest slack: 3.417 ns; Smallest slack: 3.417 ns; Relative Skew: 0.000 ns; -----------------------------------------------+-------------+-------------+ PAD | Slack |Relative Skew| -----------------------------------------------+-------------+-------------+ out_pci_req | 3.417| 0.000| -----------------------------------------------+-------------+-------------+ TIMEGRP "ram_out" OFFSET = OUT 15 ns AFTER COMP "in_pci_clock"; Largest slack: 7.367 ns; Smallest slack: 0.775 ns; Relative Skew: 6.592 ns; -----------------------------------------------+-------------+-------------+ PAD | Slack |Relative Skew| -----------------------------------------------+-------------+-------------+ io_ram_data<0> | 4.603| 2.764| io_ram_data<1> | 2.561| 4.806| io_ram_data<2> | 0.775| 6.592| io_ram_data<3> | 2.224| 5.143| io_ram_data<4> | 1.855| 5.512| io_ram_data<5> | 1.964| 5.403| io_ram_data<6> | 4.381| 2.986| io_ram_data<7> | 2.088| 5.279| io_ram_data<8> | 4.571| 2.796| io_ram_data<9> | 4.257| 3.110| io_ram_data<10> | 4.801| 2.566| io_ram_data<11> | 1.322| 6.045| io_ram_data<12> | 1.016| 6.351| io_ram_data<13> | 1.046| 6.321| io_ram_data<14> | 4.631| 2.736| io_ram_data<15> | 4.252| 3.115| io_ram_data<16> | 1.306| 6.061| io_ram_data<17> | 2.135| 5.232| io_ram_data<18> | 2.641| 4.726| io_ram_data<19> | 3.500| 3.867| io_ram_data<20> | 1.820| 5.547| io_ram_data<21> | 2.630| 4.737| io_ram_data<22> | 1.557| 5.810| io_ram_data<23> | 2.583| 4.784| io_ram_data<24> | 1.809| 5.558| io_ram_data<25> | 1.407| 5.960| io_ram_data<26> | 4.093| 3.274| io_ram_data<27> | 2.094| 5.273| io_ram_data<28> | 4.558| 2.809| io_ram_data<29> | 2.297| 5.070| io_ram_data<30> | 2.086| 5.281| io_ram_data<31> | 1.795| 5.572| out_ram_address<0> | 1.222| 6.145| out_ram_address<1> | 1.794| 5.573| out_ram_address<2> | 7.315| 0.052| out_ram_address<3> | 7.352| 0.015| out_ram_address<4> | 7.352| 0.015| out_ram_address<5> | 7.344| 0.023| out_ram_address<6> | 2.386| 4.981| out_ram_address<7> | 1.493| 5.874| out_ram_address<8> | 7.367| 0.000| out_ram_address<9> | 7.352| 0.015| out_ram_address<10> | 2.830| 4.537| out_ram_bank<0> | 1.954| 5.413| out_ram_bank<1> | 1.758| 5.609| out_ram_col_address | 7.330| 0.037| out_ram_row_address | 7.345| 0.022| out_ram_write_enable | 7.330| 0.037| -----------------------------------------------+-------------+-------------+ Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 90849 paths, 0 nets, and 10761 connections Design statistics: Minimum period: 23.193ns (Maximum frequency: 43.116MHz) Minimum input required time before clock: 5.738ns Minimum output required time after clock: 14.225ns Analysis completed MON 22 OCT 17:41:55 2007 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 147 MB